library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity GetaktetOhneProzess is Port ( clk : in STD_LOGIC; a : out STD_LOGIC; b : in STD_LOGIC; c : in STD_LOGIC; d : in STD_LOGIC; e : in STD_LOGIC); end GetaktetOhneProzess; architecture Behavioral of GetaktetOhneProzess is begin a <= '0' when b='1' else c and d when e='1' and rising_edge(clk); end Behavioral;