----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    12:31:34 05/22/2010 
-- Design Name: 
-- Module Name:    TLC - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity TLC is
    Port ( Clk : in  STD_LOGIC;
           RN : out  STD_LOGIC;
           YN : out  STD_LOGIC;
           GN : out  STD_LOGIC;
           RE : out  STD_LOGIC;
           YE : out  STD_LOGIC;
           GE : out  STD_LOGIC);
end TLC;

architecture Behavioral of TLC is

component Tunit
    port(  Clk: in std_logic;
           T: out std_logic);
end component;

component Stage_Reg
    port(Clk,T: in std_logic;
           a : out  STD_LOGIC;
           b : out  STD_LOGIC;
           c : out  STD_LOGIC;
           d : out  STD_LOGIC;
           e : out  STD_LOGIC;
           f : out  STD_LOGIC);
end component;

signal T: std_logic;
signal a: std_logic;
signal b: std_logic;
signal c: std_logic;
signal d: std_logic;
signal e: std_logic;
signal f: std_logic;

begin

M1: Tunit port map(Clk,T);
M2: Stage_Reg port map(Clk,T,a,b,c,d,e,f);

RN<=a;
YN<=b;
GN<=c;
RE<=d;
YE<=e;
GE<=f;
end Behavioral;

################################################################


Component: Tunit


----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    13:03:21 05/22/2010 
-- Design Name: 
-- Module Name:    Tunit - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity Tunit is
    Port ( Clk : in  STD_LOGIC;
           T : out  STD_LOGIC);
end Tunit;

architecture Behavioral of Tunit is

signal i: integer range 0 to 1500000000 :=0;
       type State_sequence is (stateA,stateB,stateC,stateD);
       signal State: State_sequence:=stateA;
              
begin
    
Timing: process (Clk)

begin
   if(Clk'event and Clk='1') then
      case state is
         when stateA=>
            if(i=500000000) then state <= stateB; 
               i<=0;
               else i<=i+1;
            end if;
         when stateB=>
            if(i=100000000) then state <= stateC; 
               i<=0;
               else i<=i+1;
            end if; 
        when stateC=>
            if(i=1500000000) then state <= stateD;
               i<=0;
               else i<=i+1;
            end if;
        when stateD=>
            if(i=100000000) then state <= stateA; 
               i<=0;
               else i<=i+1;
            end if;            
     end case;
    end if; 
end process;

with State select
      T <= '0' when stateA|stateC,
            '1' when others;

end Behavioral;

################################################################

Component: Stage_Reg 

----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    13:04:11 05/22/2010 
-- Design Name: 
-- Module Name:    Stage_Reg - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity Stage_Reg is
    Port ( Clk : in  STD_LOGIC;
			   T : in  STD_LOGIC;
           a : out  STD_LOGIC;
           b : out  STD_LOGIC;
           c : out  STD_LOGIC;
           d : out  STD_LOGIC;
           e : out  STD_LOGIC;
           f : out  STD_LOGIC);
end Stage_Reg;

architecture Behavioral of Stage_Reg is

type State_sequence is (stateA,stateB,stateC,stateD);
       signal State: State_sequence;
       signal lights : std_logic_vector(5 downto 0);
begin
    
State_Register: process (Clk)

begin
   if(Clk'event and Clk='1') then
      case state is
         when stateA=>
            if(T='1') then state <= stateB; end if;
         when stateB=>
            if(T='0') then state <= stateC; end if; 
        when stateC=>
            if(T='1') then state <= stateD; end if;
        when stateD=>
            if(T='0') then state <= stateA; end if;            
     end case;
    end if; 
end process;

with State select
      lights <= "100001" when stateA,
                "100010" when stateB,
                "001100" when stateC,
                "010100" when others;
             
(a,b,c,d,e,f) <= lights;


end Behavioral;


################################################################


UCF-Datein:

NET "RN" LOC = "D11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "YN" LOC = "C11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "GN" LOC = "F11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "RE" LOC = "E11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "YE" LOC = "E12" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "GE" LOC = "F12" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;