library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use Ieee.std_logic_unsigned.all; entity vga is port ( clk48_i : in std_logic; reset_i : in std_logic; rgb_o : out std_logic_vector(3 downto 0); horisync_o : out std_logic := '0'; vertisync_o : out std_logic := '0'; oenable_o : out std_logic; wenable_o : out std_logic; flash_o : out std_logic_vector(18 downto 0) := (others => '0'); data_i : in std_logic_vector(7 downto 0)); end vga; architecture rtl of vga is signal clk24_s : std_logic := '0'; signal pixel_s : std_logic_vector(9 downto 0) := (others => '0'); signal zeile_s : std_logic_vector(9 downto 0) := (others => '0'); signal flashaddress_s : std_logic_vector(18 downto 0) := (others => '0'); signal function_s : std_logic := '0'; signal memory_s : std_logic_vector(7 downto 0) := (others => '0'); --Erzeugt von 48MHz den 24MHz Takt begin process (clk48_i, reset_i) begin if reset_i = '0' then clk24_s <= '0'; elsif clk48_i'event and clk48_i = '1' then clk24_s <= not(clk24_s); end if; end process; ------------------------------------------------------------------------------ --Erhöht Pixel um 1. Bei 799 setzt es Pixel auf 0 und erhöht Zeile um 1 process (clk48_i, reset_i) begin if reset_i = '0' then pixel_s <= (others => '0'); zeile_s <= (others => '0'); vertisync_o <= '0'; elsif clk48_i'event and clk48_i = '1' then if clk24_s = '1' then pixel_s <= pixel_s + 1; if pixel_s = 799 then pixel_s <= (others => '0'); zeile_s <= zeile_s + '1'; vertisync_o <= '1'; if zeile_s = 523 then zeile_s <= (others => '0'); vertisync_o <= '0'; elsif zeile_s < 1 then vertisync_o <= '0'; end if; end if; end if; end if; end process; -------------------------------------------------------------------------------- --Wenn Pixel zwischen 111 und 750 ist werden die Daten aus dem Flash in memory_s kopiert und an rgb_o --übergeben. process(clk48_i, reset_i) begin if reset_i = '0' then rgb_o <= "0000"; function_s <= '0'; memory_s <= (others => '0'); flashaddress_s <= (others => '0'); flash_o <= (others => '0'); elsif clk48_i'event and clk48_i = '1' then if clk24_s = '1' then if (pixel_s < 110) or (zeile_s <= 12) or (zeile_s >= 493) then rgb_o <= "0000"; elsif (pixel_s >= 111) and (pixel_s <= 750) then if function_s = '0' then memory_s <= data_i; rgb_o <= memory_s (3 downto 0); flashaddress_s <= flashaddress_s + '1'; flash_o <= flashaddress_s; function_s <= '1'; elsif function_s = '1' then rgb_o <= memory_s (7 downto 4); function_s <= '0'; end if; if flashaddress_s >= 153600 then flashaddress_s <= (others => '0'); end if; elsif (pixel_s >= 751) and (pixel_s <= 799) then rgb_o <= "0000"; else rgb_o <= "0000"; end if; end if; end if; end process; ----------------------------------------------------------------------------------- --Steuert das hsync-Signal. Bei Pixelpunkte=799 setzt es hsync auf low. process (clk48_i, reset_i) begin if reset_i = '0' then horisync_o <= '0'; elsif clk48_i'event and clk48_i = '1' then if clk24_s = '1' then if (pixel_s = 799 or pixel_s < 95) then horisync_o <= '0'; else horisync_o <= '1'; end if; end if; end if; end process; oenable_o <= '0'; wenable_o <= '1'; end rtl;