Counter Project Status (08/05/2010 - 10:23:27)
Project File: Counter.ise Implementation State: Placed and Routed
Module Name: main
  • Errors:
No Errors
Target Device: xc4vlx25-11sf363
  • Warnings:
19 Warnings
Product Version:ISE 11.5
  • Routing Results:
All Signals Completely Routed
Design Goal: Balanced
  • Timing Constraints:
All Constraints Met
Design Strategy: Xilinx Default (unlocked)
  • Final Timing Score:
0 (Setup: 0, Hold: 0) (Timing Report)
 
Device Utilization Summary [-]
Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Flip Flops 4 21,504 1%  
Number of 4 input LUTs 3 21,504 1%  
Number of occupied Slices 2 10,752 1%  
    Number of Slices containing only related logic 2 2 100%  
    Number of Slices containing unrelated logic 0 2 0%  
Total Number of 4 input LUTs 3 21,504 1%  
Number of bonded IOBs 5 240 2%  
Number of BUFG/BUFGCTRLs 1 32 3%  
    Number used as BUFGs 1      
Average Fanout of Non-Clock Nets 2.21      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentDo 5. Aug 10:17:01 2010018 Warnings0
Translation ReportCurrentDo 5. Aug 10:17:05 2010000
Map ReportCurrentDo 5. Aug 10:17:11 2010003 Infos
Place and Route ReportCurrentDo 5. Aug 10:17:25 201001 Warning4 Infos
Power Report     
Post-PAR Static Timing ReportCurrentDo 5. Aug 10:17:32 2010003 Infos
Bitgen ReportOut of DateDo 5. Aug 09:51:22 2010001 Info
 
Secondary Reports [-]
Report NameStatusGenerated
ISIM Simulator LogOut of DateDo 5. Aug 09:40:47 2010
Post-Synthesis Simulation Model ReportOut of DateDo 5. Aug 09:53:05 2010
Post-Place and Route Simulation Model ReportCurrentDo 5. Aug 13:17:43 2010

Date Generated: 08/06/2010 - 09:11:02