-------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 01:24:35 09/19/2010 -- Design Name: -- Module Name: -- Target Device: -- Tool versions: -- Description: -- -- VHDL Test Bench Created by ISE for module: Top_Level_Entity -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- -- Notes: -- This testbench has been automatically generated using types std_logic and -- std_logic_vector for the ports of the unit under test. Xilinx recommends -- that these types always be used for the top-level I/O of a design in order -- to guarantee that the testbench will bind correctly to the post-implementation -- simulation model. -------------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --USE ieee.numeric_std.ALL; ENTITY Test_Bench_a IS END Test_Bench_a; ARCHITECTURE behavior OF Test_Bench_a IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT Top_Level_Entity PORT( CLK_10MHz : IN std_logic; CLK_1MHz : OUT std_logic; CLK_10MHz_read : OUT std_logic ); END COMPONENT; --Inputs signal CLK_10MHz : std_logic := '0'; --Outputs signal CLK_1MHz : std_logic; signal CLK_10MHz_read : std_logic; -- Clock period definitions constant CLK_10MHz_period : time := 100 ns; constant CLK_1MHz_period : time := 1000 ns; constant CLK_10MHz_read_period : time := 500 ns; BEGIN -- Instantiate the Unit Under Test (UUT) uut: Top_Level_Entity PORT MAP ( CLK_10MHz => CLK_10MHz, CLK_1MHz => CLK_1MHz, CLK_10MHz_read => CLK_10MHz_read ); -- Clock process definitions CLK_10MHz_process :process begin CLK_10MHz <= '0'; wait for CLK_10MHz_period/2; CLK_10MHz <= '1'; wait for CLK_10MHz_period/2; end process; -- CLK_1MHz_process :process -- begin -- CLK_1MHz <= '0'; -- wait for CLK_1MHz_period/2; -- CLK_1MHz <= '1'; ---- wait for CLK_1MHz_period/2; -- end process; -- CLK_10MHz_read_process :process -- begin -- CLK_10MHz_read <= '0'; -- wait for CLK_10MHz_read_period/2; -- CLK_10MHz_read <= '1'; -- wait for CLK_10MHz_read_period/2; -- end process; -- Stimulus process stim_proc: process begin -- hold reset state for 100 ns. wait for 100 ns; wait for CLK_10MHz_period*10; -- insert stimulus here wait; end process; END;