Timing constraint: TS_XLXI_167_CLKDV_BUF_0 = PERIOD TIMEGRP "XLXI_167_CLKDV_BUF_0" TS_CLK_TSW_P / 10 HIGH 50%; 27974 paths analyzed, 879 endpoints analyzed, 17 failing endpoints 17 timing errors detected. (17 setup errors, 0 hold errors, 0 component switching limit errors) Minimum period is 109.150ns. -------------------------------------------------------------------------------- Slack (setup path): -2.275ns (requirement - (data path - clock path skew + uncertainty)) Source: XLXI_111/XLXI_1/XLXI_1/BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_almost_full_i (FF) Destination: XLXI_111/XLXI_1/XLXI_13/rd_state_4 (FF) Requirement: 2.000ns Data Path Delay: 4.000ns (Levels of Logic = 3)(Component delays alone exceeds constraint) Clock Path Skew: -0.033ns (5.240 - 5.273) Source Clock: CLK_250MHz rising at 48.000ns Destination Clock: CLK_CTRL rising at 50.000ns Clock Uncertainty: 0.242ns Clock Uncertainty: 0.242ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.000ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.204ns Phase Error (PE): 0.140ns Maximum Data Path: XLXI_111/XLXI_1/XLXI_1/BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_almost_full_i to XLXI_111/XLXI_1/XLXI_13/rd_state_4 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X21Y129.YQ Tcko 0.338 XLXI_111/XLXI_1/almost_full XLXI_111/XLXI_1/XLXI_1/BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_almost_full_i SLICE_X19Y128.F4 net (fanout=5) 0.419 XLXI_111/XLXI_1/almost_full SLICE_X19Y128.XMUX Tif5x 0.563 XLXI_111/XLXI_1/XLXI_13/N111 XLXI_111/XLXI_1/XLXI_13/rd_state_mux0000<0>11_G XLXI_111/XLXI_1/XLXI_13/rd_state_mux0000<0>11 SLICE_X17Y126.G2 net (fanout=4) 0.651 XLXI_111/XLXI_1/XLXI_13/N111 SLICE_X17Y126.Y Tilo 0.193 XLXI_111/XLXI_1/XLXI_13/rd_state<2> XLXI_111/XLXI_1/XLXI_13/rd_state_mux0000<0>311 SLICE_X16Y127.F4 net (fanout=3) 0.338 XLXI_111/XLXI_1/XLXI_13/N41 SLICE_X16Y127.X Tilo 0.194 XLXI_111/XLXI_1/XLXI_13/rd_state_mux0000<0>28 XLXI_111/XLXI_1/XLXI_13/rd_state_mux0000<0>28 SLICE_X17Y127.SR net (fanout=1) 0.273 XLXI_111/XLXI_1/XLXI_13/rd_state_mux0000<0>28 SLICE_X17Y127.CLK Tsrck 1.031 XLXI_111/XLXI_1/XLXI_13/rd_state<4> XLXI_111/XLXI_1/XLXI_13/rd_state_4 ------------------------------------------------- --------------------------- Total 4.000ns (2.319ns logic, 1.681ns route) (58.0% logic, 42.0% route) -------------------------------------------------------------------------------- Slack (setup path): -1.565ns (requirement - (data path - clock path skew + uncertainty)) Source: XLXI_111/XLXI_1/XLXI_1/BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_almost_full_i (FF) Destination: XLXI_111/XLXI_1/XLXI_13/reading (FF) Requirement: 2.000ns Data Path Delay: 3.276ns (Levels of Logic = 2)(Component delays alone exceeds constraint) Clock Path Skew: -0.047ns (5.226 - 5.273) Source Clock: CLK_250MHz rising at 48.000ns Destination Clock: CLK_CTRL rising at 50.000ns Clock Uncertainty: 0.242ns Clock Uncertainty: 0.242ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.000ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.204ns Phase Error (PE): 0.140ns Maximum Data Path: XLXI_111/XLXI_1/XLXI_1/BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_almost_full_i to XLXI_111/XLXI_1/XLXI_13/reading Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X21Y129.YQ Tcko 0.338 XLXI_111/XLXI_1/almost_full XLXI_111/XLXI_1/XLXI_1/BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_almost_full_i SLICE_X19Y128.F4 net (fanout=5) 0.419 XLXI_111/XLXI_1/almost_full SLICE_X19Y128.XMUX Tif5x 0.563 XLXI_111/XLXI_1/XLXI_13/N111 XLXI_111/XLXI_1/XLXI_13/rd_state_mux0000<0>11_G XLXI_111/XLXI_1/XLXI_13/rd_state_mux0000<0>11 SLICE_X18Y128.G4 net (fanout=4) 0.453 XLXI_111/XLXI_1/XLXI_13/N111 SLICE_X18Y128.Y Tilo 0.194 N4 XLXI_111/XLXI_1/XLXI_13/_old_reading_23_inv1 SLICE_X19Y127.SR net (fanout=1) 0.278 XLXI_111/XLXI_1/XLXI_13/_old_reading_23_inv SLICE_X19Y127.CLK Tsrck 1.031 XLXI_111/XLXI_1/XLXI_13/reading XLXI_111/XLXI_1/XLXI_13/reading ------------------------------------------------- --------------------------- Total 3.276ns (2.126ns logic, 1.150ns route) (64.9% logic, 35.1% route) -------------------------------------------------------------------------------- Slack (setup path): -1.478ns (requirement - (data path - clock path skew + uncertainty)) Source: XLXI_111/XLXI_1/XLXI_1/BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_almost_full_i (FF) Destination: XLXI_111/XLXI_1/XLXI_13/reading (FF) Requirement: 2.000ns Data Path Delay: 3.189ns (Levels of Logic = 3)(Component delays alone exceeds constraint) Clock Path Skew: -0.047ns (5.226 - 5.273) Source Clock: CLK_250MHz rising at 48.000ns Destination Clock: CLK_CTRL rising at 50.000ns Clock Uncertainty: 0.242ns Clock Uncertainty: 0.242ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.000ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.204ns Phase Error (PE): 0.140ns Maximum Data Path: XLXI_111/XLXI_1/XLXI_1/BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_almost_full_i to XLXI_111/XLXI_1/XLXI_13/reading Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X21Y129.YQ Tcko 0.338 XLXI_111/XLXI_1/almost_full XLXI_111/XLXI_1/XLXI_1/BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_almost_full_i SLICE_X20Y127.F4 net (fanout=5) 0.431 XLXI_111/XLXI_1/almost_full SLICE_X20Y127.X Tilo 0.194 XLXI_111/XLXI_1/XLXI_13/writing XLXI_111/XLXI_1/XLXI_13/rd_reset_out_mux000061 SLICE_X21Y127.G4 net (fanout=2) 0.329 XLXI_111/XLXI_1/XLXI_13/N17 SLICE_X21Y127.Y Tilo 0.193 XLXI_111/XLXI_1/XLXI_13/rd_state<1> XLXI_111/XLXI_1/XLXI_13/rd_state_mux0000<3>29 SLICE_X21Y127.F4 net (fanout=1) 0.158 XLXI_111/XLXI_1/XLXI_13/rd_state_mux0000<3>29 SLICE_X21Y127.X Tilo 0.193 XLXI_111/XLXI_1/XLXI_13/rd_state<1> XLXI_111/XLXI_1/XLXI_13/reading_or000025 SLICE_X19Y127.BY net (fanout=2) 0.311 XLXI_111/XLXI_1/XLXI_13/reading_or0000 SLICE_X19Y127.CLK Tsrck 1.042 XLXI_111/XLXI_1/XLXI_13/reading XLXI_111/XLXI_1/XLXI_13/reading ------------------------------------------------- --------------------------- Total 3.189ns (1.960ns logic, 1.229ns route) (61.5% logic, 38.5% route) --------------------------------------------------------------------------------