library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity kompe is
    Port ( eina : in bit_vector(0 to 2);
           einb : in bit_vector(0 to 2);
	   ein :  in std_logic;
           groesser : out std_logic;
           gleich : out std_logic;
           kleiner : out std_logic);
end kompe;

architecture Behavioral of kompe is
signal einaa, einbb : bit_vector(0 to 2);

begin
   
komp: process (eina,einb,einaa,einbb)
begin

einaa<=eina;
einbb<=einb;

groesser<='1';
gleich<='1';
kleiner<='1';
				    
if(einaa > einbb) then
	 groesser <= '0';
end if;

if(einaa = einbb) then
	 gleich <= '0';
end if;

if(einaa < einbb) then
	 kleiner <= '0';
end if;
 
end process komp;

end Behavioral;