library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity abh_zaehler is
    Port ( reset : in std_logic;
           up : in std_logic;
           down : in std_logic;
           clock_in : in std_logic;
           zaehler_out : inout std_logic_vector(9 downto 0);
           clock_out : inout std_logic);
end abh_zaehler;

architecture Behavioral of abh_zaehler is

	signal zaehler_int1 : std_logic_vector (9 downto 0);
	signal zaehler_int2 : std_logic_vector (9 downto 0);

begin


process (clock_in, reset) -- HIER FEHLERMELDUNG 
begin
   if reset='1' then 
      zaehler_int1 <= "0000000000";
   elsif (clock_in='1' and clock_in'event and up='1' and down='0') then 
          zaehler_int1 <= zaehler_int1 + 1;
   elsif (clock_in='1' and clock_in'event and up='0' and down='1') then
          zaehler_int1 <= zaehler_int1 - 1;
   end if;
end process;


process (clock_in, reset)
begin
	if reset='1' then 
     	zaehler_int2 <= "0000000000";
	elsif clock_in='1' and clock_in'event then
	--	zaehler_int <= zaehler_out;
		
		while (zaehler_int2 > "0000000000") loop
			zaehler_int2 <= zaehler_int2 - 1;
		end loop;

		if zaehler_int2 = "0000000000" then
			zaehler_int2 <= zaehler_int1;
			clock_out <= not clock_out;
		end if;
			
	end if;
end process;

zaehler_out <= zaehler_int1;

end Behavioral;