library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity led is
    Port ( reset : in std_logic;
           clock : in std_logic;
           verzoeg : in std_logic_vector(9 downto 0);
           led_segm : out std_logic_vector(6 downto 0);
           led_ziff : inout std_logic_vector(3 downto 0));
end led;

architecture Behavioral of led is

   -- BCD-zu-7-Segment Decoder Funktion -------------------------------------
   function bcd_to_7seg( cnt : std_logic_vector(9 downto 0))
      return std_logic_vector
   is
      variable res : std_logic_vector(6 downto 0);
   begin
      case cnt is
         when "0000000000" => res := "1111110";                                                   
         when "0000000001" => res := "0110000";                                                   
         when "0000000010" => res := "1101101";                                                   
         when "0000000011" => res := "1111001";                                                   
         when "0000000100" => res := "0110011";                                                   
         when "0000000101" => res := "1011011";                                                   
         when "0000000110" => res := "0011111";                                                   
         when "0000000111" => res := "1110000";                                                   
         when "0000001000" => res := "1111111";                                                   
         when "0000001001" => res := "1110011";                                                   
         when "0000001010" => res := "1110111"; -- Decodierung > 9 wird nicht benoetigt,          
         when "0000001011" => res := "0011111"; -- kostet aber auch keine zusaetzlichen Ressourcen
         when "0000001100" => res := "1001110";                                                   
         when "0000001101" => res := "0111101";                                                   
         when "0000001110" => res := "1001111";                                                   
         when "0000001111" => res := "1000111";
         when others => res := "1111111"; -- nur fuer Simulation
      end case;
      return res;
   end;
   -- bei groesseren Designs wuerde man die Funktion in ein Package auslagern
   --------------------------------------------------------------------------



begin

--	if reset ='1' then
--		led_segm <= "0000000";	  --einzelne segmente auf 0 setzen
--		led_ziff <= "0000";		  --alle ziffern auf 0 setzen
--	elsif (clock = '1' and clock'Event) then

		

   -- Multiplex-Steuerung
   -- Die Digit-Treiber sind pnp-Transistoren und benoetigen
   -- ein L-Signal, damit die entspr. 7-Seg-Anzeige leuchtet
	process(reset, clock)
	begin
	 if reset = '1' then led_ziff <= "1111";
      elsif clock='1' and clock'event then
         case led_ziff is
            when "1110" => led_ziff <= "0111"; -- 0 = Digit-Treiber aktiv
            when "0111" => led_ziff <= "1011";
            when "1011" => led_ziff <= "1101";
            when "1101" => led_ziff <= "1110";
            when others => led_ziff <= (others=>'1'); -- alles AUS
         end case;
      else
         led_ziff <= (others=>'1');
      end if;
	end process;
	
	--segmentsteuerung
	process(reset, clock)
	variable var_led_segment: STD_LOGIC_VECTOR (9 downto 0);
     begin
		if reset = '1' then led_ziff <= "1111";
		elsif clock='1' and clock'event then
			
			var_led_segment := verzoeg;

			if led_ziff = "0111" then   --tausender stelle ermitteln
				led_segm <= bcd_to_7seg (var_led_segment / 1000);
			end if;

		end if;

	end process;
		

--	end if;

end Behavioral;