library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity fkt_gen_top is
    Port ( reset : in std_logic;
           clock : in std_logic;
           taste_up : in std_logic;
           taste_down : in std_logic;
           signal_wahl : in std_logic;
           analog_out : out std_logic_vector(7 downto 0));
end fkt_gen_top;

architecture Behavioral of fkt_gen_top is

signal div_clk : std_logic;
signal zaehler : std_logic_vector ( 7 downto 0);

--signal deb_up : std_logic;
--signal deb_dw : std_logic;
--signal abh_clock : std_logic;


   COMPONENT counter_top
   PORT( deb_up	:	OUT	STD_LOGIC; 
          reset	:	IN	STD_LOGIC; 
          clock	:	IN	STD_LOGIC; 
          t_runter	:	IN	STD_LOGIC; 
          t_hoch	:	IN	STD_LOGIC; 
          abh_clock	:	OUT	STD_LOGIC; 
          count	:	INOUT	STD_LOGIC_VECTOR (7 DOWNTO 0); 
          XLXN_31	:	INOUT	STD_LOGIC_VECTOR (9 DOWNTO 0); 
          deb_dw	:	OUT	STD_LOGIC; 
          clk_div_95	:	OUT	STD_LOGIC; 
          clk_div_6k	:	OUT	STD_LOGIC; 
          clk_div_781k	:	OUT	STD_LOGIC);
   END COMPONENT;

   COMPONENT mux_top
   PORT( count	:	IN	STD_LOGIC_VECTOR (7 DOWNTO 0); 
          div_clock_in	:	IN	STD_LOGIC; 
          reset	:	IN	STD_LOGIC; 
          schalter_signwahl	:	IN	STD_LOGIC; 
          a_out	:	OUT	STD_LOGIC_VECTOR (7 DOWNTO 0));
   END COMPONENT;

begin

   UUT: counter_top PORT MAP( 
		reset => reset, 
		clock => clock, 
		t_runter => taste_down, 
		t_hoch => taste_up, 
--		abh_clock => , 
		count => zaehler, 
--		XLXN_31 => , 
--		deb_dw => ,
--		deb_up => , 
--		clk_div_95 => , 
		clk_div_6k => div_clk
--		clk_div_781k => 
   );

   UUT: mux_top PORT MAP(
		count => zaehler, 
		div_clock_in => div_clk, 
		reset => reset, 
		schalter_signwahl => signal_wahl, 
		a_out => analog_out
   );

end Behavioral;