clk_gen: process(clk, reset) 
		variable var_conv: std_logic;
		variable var_conv_wert : std_logic_vector(10 downto 0);

		variable var_sck: std_logic;	
		variable var_sck_wert: std_logic_vector(5 downto 0);	
	
		variable var_ld: std_logic;						 			
		variable var_ld_wert: std_logic_vector(10 downto 0);

		variable var_cs_ld: std_logic;
		variable var_cs_ld_wert: std_logic_vector(10 downto 0);
		
		begin
		sdi<='0';			  			
		
	
		if(reset = '0') then

			conv <= '1';
			var_conv := '1';
			var_conv_wert := "00000000000";
				
			var_sck_wert := "000000";
			var_sck := '1';
			sck <= '1';
				
			var_ld := '1';
			var_ld_wert := "00000000000";
			ld_piso <= '1';
				
			cs_ld <= '1';
			var_cs_ld := '1';
			var_cs_ld_wert := "00011001000";
			
			elsif(clk = '1' and clk'event) then
				
				var_conv_wert := var_conv_wert + '1';
				var_sck_wert := var_sck_wert + '1';
				var_ld_wert := var_ld_wert + '1';
				var_cs_ld_wert := var_cs_ld_wert + '1';
		end if;