library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity frequenzteiler is
    Port ( clock_32MHz : in std_logic;
		reset : in std_logic;
           clock_1MHz : out std_logic;
           clock_100kHz : out std_logic;
           clock_10kHz : out std_logic;
--           clock_1kHz : out std_logic;
--           clock_100Hz : out std_logic;
--           clock_50Hz : out std_logic;
--           clock_10Hz : out std_logic;
--           clock_1Hz : out std_logic;
--           clock_500mHz : out std_logic);
end frequenzteiler;

architecture Behavioral of frequenzteiler is

			signal	clock_1MHz_int, clock_11MHz_int, clock_100kHz_int, clock_10kHz_int : std_logic;			
			signal	clock_1kHz_int, clock_100Hz_int, clock_10Hz_int : std_logic;
			signal	clock_1Hz_int, clock_50Hz_int, clock_500mHz_int : std_logic;

begin

					clock_1MHz <= clock_1MHz_int;
					clock_100kHz <= clock_100kHz_int;
					clock_10kHz <= clock_10kHz_int;
--					clock_1kHz <= clock_1kHz_int;
--					clock_100Hz <= clock_100Hz_int;
--					clock_10Hz <= clock_10Hz_int;
--					clock_50Hz <= clock_50Hz_int;
--					clock_1Hz <= clock_1Hz_int;
--					clock_500mHz <= clock_500mHz_int;

 -- Erzeugung von 1MHz

  			process (reset, clock_32MHz)
			variable Z : integer range 0 to 31;
				begin
					if (reset = '1') then 
							Z := 0;
							clock_1MHz_int <= '0';
						elsif (clock_32MHz = '1') and (clock_32MHz'event) then
							if Z < 31 then
								Z := Z+1;
								else Z := 0;
							end if;
							if Z = 31 then clock_1MHz_int <= '1';
								else clock_1MHz_int <= '0';
							end if;
					end if;
			end process;

 -- Erzeugung von 100kHz

			process (reset, clock_32MHz, clock_1MHz_int)
			variable Z : integer range 0 to 9;
				begin
					if clock_100kHz_int = 'U' then clock_100kHz_int <= '0';
					end if;
					if (reset = '1') then 
							Z := 0;
							clock_100kHz_int <= '0';
						elsif (clock_32MHz = '1' and clock_32MHz'event) and (clock_1MHz_int = '1') then
							if Z < 9 then
								Z := Z+1;
								else Z := 0;
							end if;
							if (Z = 9) then 
									clock_100kHz_int <= '1';
								else clock_100kHz_int <= '0';
							end if;
					end if;
			end process;

 -- Erzeugung von 10kHz

			process (reset, clock_32MHz, clock_100kHz_int)
			variable Z : integer range 0 to 9;
				begin
					if clock_10kHz_int = 'U' then clock_10kHz_int <= '0';
					end if;
					if (reset = '1') then 
							Z := 0;
							clock_10kHz_int <= '0';
						elsif (clock_32MHz = '1' and clock_32MHz'event) and (clock_100kHz_int = '1') then
							if Z < 9 then
								Z := Z+1;
								else Z := 0;
							end if;
							if (Z = 9) then 
									clock_10kHz_int <= '1';
								else clock_10kHz_int <= '0';
							end if;
					end if;
			end process;

  
end Behavioral;