library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;


entity simple_counter is
    Port ( 
	 output 	: out std_logic_vector(6 downto 0);
	 clk		: in std_logic	
	 );
end simple_counter;

architecture Behavioral of simple_counter is
Signal next_state : std_logic_vector(6 downto 0);
begin

--count: Process (clk)
--variable counter : integer range 0 to 115; 
--begin

--	if (clk='1' and clk'event) then
--	counter:=counter+1;
--	end if;
	
--	output<=conv_std_logic_Vector(counter,output'length);
--end Process count;

count: Process (clk)
variable counter  : std_logic_vector(6 downto 0);   
begin
	
case counter is
when "1110011" => next_state<=(others=>'0');
when others   => next_state<=counter+1; 
end case;

if (clk='1' and clk'event) then
counter:=next_state;
end if;
	
output<=counter;
end Process count;


end Behavioral;