library ieee; use ieee.std_logic_1164.all; entity lcd_daten_tb is end entity lcd_daten_tb; architecture testbench of lcd_daten_tb is constant clk_period : time := (1 sec)/(50_000_000) ; component lcd_daten is port( clk : in std_logic; reset : in std_logic:= '1'; o_rs : out std_logic; o_rw : out std_logic; o_e : out std_logic; o_csb : out std_logic; o_cs : out std_logic; o_data : out std_logic_vector(7 downto 0) ); end component lcd_daten; signal tb_clk : std_logic := '1'; signal tb_reset : std_logic := '1'; signal tb_o_rs : std_logic; signal tb_o_rw : std_logic; signal tb_o_e : std_logic; signal tb_o_csb : std_logic; signal tb_o_cs : std_logic; signal tb_o_data : std_logic_vector(7 downto 0); begin dut: lcd_daten port map ( clk => tb_clk, -- : in std_logic; reset => tb_reset, -- : in std_logic:= '1'; o_rs => tb_o_rs, -- : out std_logic; o_rw => tb_o_rw, -- : out std_logic; o_e => tb_o_e, -- : out std_logic; o_csb => tb_o_csb, -- : out std_logic; o_cs => tb_o_cs, -- : out std_logic; o_data => tb_o_data -- : out std_logic_vector(7 downto 0) ); tb_clk <= not tb_clk after clk_period/2; tb_reset <= '0', '1' after 5*clk_period; end testbench;