LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.All; USE IEEE.NUMERIC_STD.ALL; USE IEEE.STD_LOGIC_SIGNED.ALL; ENTITY Sinusgenerator IS PORT(clk : IN std_logic; clk_adc : BUFFER std_logic; clk_dac : OUT std_logic; reset : IN std_logic; Sinusgenerator_output : BUFFER std_logic_vector(13 DOWNTO 0) ); END Sinusgenerator; ARCHITECTURE rtl OF Sinusgenerator IS ------------------------ Definitionen für Tiefpass ----------------------------- SIGNAL enable : bit; SIGNAL clk_enable : bit; CONSTANT K1 : signed(14 DOWNTO 0) := to_signed(31162, 15); -- K1 = 1.902 CONSTANT C : signed(14 DOWNTO 0) := to_signed(10125, 15); -- C = 0.309 SIGNAL latch1 : signed(14 DOWNTO 0); SIGNAL latch2 : signed(14 DOWNTO 0); SIGNAL ykT : signed(14 DOWNTO 0); SIGNAL ykT_T_help : signed(29 DOWNTO 0); SIGNAL ykT_T : signed(14 DOWNTO 0); SIGNAL ykT_2T : signed(14 DOWNTO 0); ALIAS ykT_help_15 : signed(14 DOWNTO 0) IS ykT_T_help(29 DOWNTO 15); ALIAS ykT_ausgabe : signed(13 DOWNTO 0) IS ykT(14 DOWNTO 1); ------------------------------ Beginn des Programms ----------------------------- BEGIN clk_dac <= clk; -- Clock für D/A-Wandler ykT_T_help <= K1*ykT_T; -- Gleichungen für ykT <= ykT_help_15 - ykT_2T; -- Sinusgenerator Clock_AD: process(clk,reset) -- Clock für A/D-Wandler BEGIN if (reset='0') then clk_enable<='0'; ELSIF (clk'event AND clk = '1') THEN clk_enable <= NOT enable; END IF; END process Clock_AD; Clock_AD2: process(clk,reset) -- Clock für A/D-Wandler BEGIN if (reset='0') then clk_adc<='0'; ELSIF (clk'event AND clk = '1') THEN if clk_enable = '1' then clk_adc <= NOT clk_adc; end if; END IF; END process Clock_AD2; Speicher: process(clk,reset) -- Speicher BEGIN IF (reset = '0') THEN -- über Taster Anfangswert speichern, latch1 <= C; -- da default-value ignoriert wird ELSIF (clk'event AND clk = '1') THEN ykT_T <= latch1; latch1 <= ykT; enable <= NOT enable; END IF; END process Speicher; Speicher2: process(clk,reset) -- Speicher if reset='0' then ykT_2T<=(others=>'0'); latch2<=(others=>'0'); ELSIF (clk'event AND clk = '1') THEN if (enable='1') then ykT_2T <= latch2; latch2 <= ykT_T; end if; END IF; END process Speicher; Sinusgenerator_output <= std_logic_vector(ykT_ausgabe); -- Ausgabe auf D/A-Wandler END rtl;