library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity dsf is	
end dsf;

architecture Behavioral of dsf is

signal			clock: 				 std_logic := '1';
signal			audio_reset_b: 	 std_logic := '1';
signal			ac97_sdata_out: 	 std_logic := '0';
signal			ac97_sdata_in: 	 std_logic := '0';
signal			ac97_synch: 		 std_logic := '0';
signal			ac97_bit_clock: 	 std_logic := '0';



signal Kommando	: std_logic_vector (56 downto 0) := "011100000000000000000001100000000000000000000000000000000"; --Erstes Kommando: 
																	  --
signal shift_reg	: std_logic_vector (56 downto 0) := "011100000000000000000001100000000000000000000000000000000";
signal pwmvalue	: integer range 0 to 16 := 16; 
signal cnt	 		: integer range 0 to 255 := 255;
signal pwmvalue2	: integer range 0 to 255 := 255; 
signal cnt2	 		: integer range 0 to 255 := 0;
signal puls			: std_logic := '0';




begin

process begin
      wait until rising_edge(ac97_bit_clock);
      -- Zähler         
      if (cnt<255) then cnt <= cnt+1;
      else              cnt <= 0;
      end if;      
      -- Vergleicher
      if (cnt>=(pwmvalue)) then 			ac97_synch <= '0';
      else                             ac97_synch <= '1';
      end if;
end process;

process begin
      wait until rising_edge(ac97_bit_clock);
      -- Zähler         
      if (cnt2<255) then cnt2 <= cnt2+1;
      else              cnt2 <= 0;
      end if;      
      -- Vergleicher
      if (cnt2>=(pwmvalue2)) then 			puls <= '1';
      else                             puls <= '0';
      end if;
end process;

process begin
wait until rising_edge(ac97_bit_clock);
if puls'event then
shift_reg <= Kommando;
elsif (ac97_bit_clock'event and ac97_bit_clock = '1') then
ac97_sdata_out <= shift_reg(56);
shift_reg(56 downto 1) <= shift_reg(55 downto 0);
end if;
end process;

process begin
  ac97_bit_clock <= '0';
  wait for 5 ns;
  ac97_bit_clock <= '1';
  wait for 5 ns;
end process;



end Behavioral;