library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity dsf is	
				
end dsf;

architecture Behavioral of dsf is

signal			ac97_sdata_out: 	 std_logic := '0';

signal audio_reset_b_MM: 		std_logic := '1';
signal ac97_sdata_out2_MM: 	std_logic := '0';
signal ac97_synch_MM: 			std_logic := '0';
signal ac97_bit_clock_MM: 		std_logic := '0';

signal				audio_reset_b:  	 	std_logic; 
signal				ac97_sdata_out2:  	std_logic; 
signal				ac97_synch:  		 	std_logic; 
signal				ac97_bit_clock:  	 	std_logic; 
signal				audio_reset_b_M: 		std_logic;
signal				ac97_sdata_out2_M: 	std_logic;
signal				ac97_synch_M: 			std_logic;
signal				ac97_bit_clock_M: 	std_logic;

																			              --						 --
signal Kommando	: std_logic_vector (56 downto 0) := "011100000000000000001101000000000000000000100000001000000"; --RecordSelect-Register 0x1A, Line-L/R als ADC-Source 
signal Kommando1	: std_logic_vector (56 downto 0) := "011100000000000000001110000000000000000001111000011110000"; --RecordGain-Register 0x1C, Max. Gain für Line L/R
signal Kommando2	: std_logic_vector (56 downto 0) := "011100000000000000001000000000000000000000000000000000000"; --MixerInput-Register 0x10, LineIn L/R als Mixerquelle

signal shift_reg	: std_logic_vector (56 downto 0) := "001110000000000000000000100000000000000000000000000000000"; --LineOut-Register 0x02h, Lauteste Einstellung und Unmuted
signal pwmvalue	: integer range 0 to 16 := 16; 
signal cnt	 		: integer range 0 to 255 := 255;
signal pwmvalue2	: integer range 0 to 255 := 254; 
signal cnt2	 		: integer range 0 to 255 := 0;
signal puls			: std_logic := '0';

signal framezaehler	: std_logic_vector (2 downto 0) := "000";

signal und_eingang	: std_logic := '1';


begin

process begin
      wait until rising_edge(ac97_bit_clock_MM);
      -- Zähler         
      if (cnt<255) then cnt <= cnt+1;
      else              cnt <= 0;
      end if;      
      -- Vergleicher
      if (cnt>=(pwmvalue)) then 			ac97_synch_MM <= '0';
      else                             ac97_synch_MM <= '1';
      end if;
end process;

process begin
      wait until rising_edge(ac97_bit_clock_MM);
      -- Zähler         
      if (cnt2<255) then cnt2 <= cnt2+1;
      else              cnt2 <= 0;
      end if;      
      -- Vergleicher
      if (cnt2>=(pwmvalue2)) then 			puls <= '1';
      else                             puls <= '0';
      end if;
end process;

process (puls) 
	begin
   if puls='1' and puls'event then
      framezaehler <= framezaehler + 1;
   end if;
end process;

process begin
wait until rising_edge(ac97_bit_clock_MM);
if puls = '1' then
case framezaehler is		
			when "001" => 
			shift_reg <= Kommando;
			when "010" => 
			shift_reg <= Kommando1;
			when "011" => 
			shift_reg <= Kommando2;
			when others =>
			und_eingang <= '0';
	end case;
elsif (ac97_bit_clock_MM'event and ac97_bit_clock_MM = '1') then
ac97_sdata_out <= shift_reg(56);
shift_reg(56 downto 1) <= shift_reg(55 downto 0);
end if;
end process;

ac97_sdata_out2 <= ac97_sdata_out and und_eingang;
ac97_sdata_out2_M <= ac97_sdata_out and und_eingang;

audio_reset_b <= audio_reset_b_MM; 
audio_reset_b_M <= audio_reset_b_MM;
ac97_synch <= ac97_synch_MM;
ac97_synch_M <= ac97_synch_MM;
ac97_bit_clock_MM <= ac97_bit_clock;
ac97_bit_clock_M <= ac97_bit_clock_MM;

process begin
  ac97_bit_clock <= '0';
  wait for 5 ns;
  ac97_bit_clock <= '1';
  wait for 5 ns;
end process;

end Behavioral;