library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; use ieee.numeric_std.all; entity tb_Sinc3_Filter is end tb_Sinc3_Filter; architecture TESTBENCH of tb_Sinc3_Filter is signal RESN1 : std_logic; signal MOUT1 : std_logic; signal CLK1 : std_logic; signal CNR1 : std_logic; signal UP : std_logic; signal COUNTER : std_logic_vector(24 downto 0); COMPONENT Sinc3_Filter PORT ( RESN : IN STD_LOGIC; MOUT : IN STD_LOGIC; CLK : IN STD_LOGIC; CNR : IN STD_LOGIC; CN_OUT : OUT STD_LOGIC_VECTOR(24 DOWNTO 0) ); END COMPONENT; begin FUNKTION : process begin CLK1 <= '0'; CNR1 <= '0'; RESN1 <= '0'; -- Reset MOUT1 <= '0'; CNR1 <= '0'; COUNTER <= (others => '0'); UP <= '1'; loop wait for 20 ns; -- 12,5 MHz Takt CLK1 <= not CLK1; CNR1 <= not CNR1; wait for 100 ns; RESN1 <= '1'; ----------------mapping------------------------------- ----------------Rampe--------------------------------- -- if (UP = '1') then -- ZAEHLER <= ZAEHLER + 2; -- elsif (UP = '0') then -- ZAEHLER <= (others => '0'); -- else ZAEHLER <= (others => 'Z'); -- end if; -- -- if (ZAEHLER > 100) then -- UP <= '0'; -- end if; -- if (ZAEHLER <= 0) then -- UP <= '1'; -- end if; ----------------Dreieck Signal---------------------- if(UP = '1') then COUNTER <= COUNTER + 5; elsif(UP = '0') then COUNTER <= COUNTER - 1; end if; if(COUNTER > 50) then UP <= '0'; end if; if(COUNTER < 5) then UP <= '1'; end if; if UP <= '1' then MOUT1 <= '1'; else MOUT1 <= '0'; end if; end loop; end process FUNKTION; ----------------instanz---------------------------------- inst_01 : Sinc3_Filter port map(RESN1, UP, CLK1, CNR1); end TESTBENCH;