/* RC5-ATmega32 nach rc5.asm von ATMEL NORWAY Quarz 4MHz */ .INCLUDE "M32DEF.INC" .DEVICE ATmega32 .EQU INPUT = 2 //PD2 (INT0) Interrupt .EQU SYS_ADDR = 0 //System Adresse .DEF S = R0 //Storage for the Status Register SREG .DEF inttemp = R1 //temporary variable for ISR .DEF ref1 = R2 //Reference for timimg .DEF ref2 = R3 //dito .def flipflop = R4 .DEF temp = R16 //Temporary variable .DEF timerL = R17 //Timimg variable updated every 14µs .DEF timerH = R18 //Timimg variable updated every 16ms .DEF system = R19 //Address data received .DEF command = R20 //Command received .DEF bitcnt = R21 //Counter .CSEG //Prog in flash .ORG 0 RJMP reset //******************************************************************************** /* "TIM0_OVF" - Timer/counter overflow interrupt handler The overflow interrupt increments the "timerL" and "timerH" every 64µs and 16,384ms Crystal Freqency: 4MHz modifiziert auf 8MHz Number of words: 7 Number of cycles: 6 + reti Low register used: 1 High register used: 3 Pointers used: 0 */ //******************************************************************************** .ORG OVF0addr RJMP TIM0_OVF TIM0_OVF: IN S, SREG //Store SREG // com flipflop //8MHz brne TIM0_OVF_exit //8MHz // INC timerL //updated every 64µs INC inttemp BRNE TIM0_OVF_exit INC timerH //if 256th int inc timer TIM0_OVF_exit: OUT SREG, S //Restore SREG RETI //********************************************************************************* /* Initializes Timer, Ports and Interrupts Calls "detect" in an endless loop and puts the result out on PortB Number of words: 16 Low register used: 0 High register used: 3 Pointers used: 0 */ //********************************************************************************* reset: LDI temp, LOW(RAMEND)//initialize stackpointer for parts with sw stack OUT SPL, temp LDI temp, HIGH(RAMEND) OUT SPH, temp LDI temp, 1 //Timer/Counter 0 clocked at ck OUT TCCR0,temp //no prescaler LDI temp, 1< 3/4 bit time BRGE fault //exit SBIC PinD, INPUT //Wait for falling edge start bit 2 RJMP start3 CLR timerL LDI bitcnt, 12 //Receive 12 bits CLR command CLR system sample: CP timerL, ref1 //Sample INPUT at 1/4 bit time BRLO sample //Branch if Lower SBIC Pind, INPUT //Skip if Bit in I/O Register is Cleared RJMP bit_is_a_1 //Jump if line high bit_is_a_0: CLC //Store a '0' (Clear Carry Flag) ROL command //Rotate Left trough Carry //(Shifts all bits in Rd one place to the left) ROL system //Sysnchronize timimg bit_is_a_0a: CP timerL, ref2 //If no edge within 3/4 bit time (Compare) BRGE fault //exit (Branch if Greater or Equal (Signed)) SBIS PinD, INPUT //wait for rising edge RJMP bit_is_a_0a //in the middle of the bit CLR timerL RJMP nextbit bit_is_a_1: SEC //Store a '1' (Set Carry Flag) ROL command //Rotate Left trough Carry //(Shifts all bits in Rd one place to the left) ROL system //Sysnchronize timimg bit_is_a_1a: CP timerL, ref2 //If no edge within 3/4 bit time BRGE fault //exit SBIC PinD, INPUT //waiting for falling edge RJMP bit_is_a_1a //in the middle of the bit CLR timerL nextbit: DEC bitcnt //if bitcnt > 0 BRNE sample //get next bit //All bits sucessfully received? MOV temp, command //Place system bits in "system" ROL temp ROL system ROL temp ROL system BST system, 5 //Move toggle bit "to command" //Bit Store from Bit in Register to //T Flag in SREG BLD command, 6 //siehe oben //Clear remaining bits restlich bits löschen ANDI command, 0b01111111 ANDI system, 0x1F RET fault: SER command //Both "command" and "system" SER system //0xFF indicates failure RET .EXIT