| Environment Settings | ||||
| Environment Variable | xst | ngdbuild | map | par |
| PATHEXT | .COM; .EXE; .BAT; .CMD; .VBS; .VBE; .JS; .JSE; .WSF; .WSH |
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| Path | E:\Programme\Xilinx\ISE\12.3\ISE_DS\ISE\\lib\nt; E:\Programme\Xilinx\ISE\12.3\ISE_DS\ISE\\bin\nt; E:\Programme\Xilinx\ISE\12.3\ISE_DS\PlanAhead\bin; E:\Programme\Xilinx\ISE\12.3\ISE_DS\ISE\bin\nt; E:\Programme\Xilinx\ISE\12.3\ISE_DS\ISE\lib\nt; E:\Programme\Xilinx\ISE\12.3\ISE_DS\EDK\bin\nt; E:\Programme\Xilinx\ISE\12.3\ISE_DS\EDK\lib\nt; E:\Programme\Xilinx\ISE\12.3\ISE_DS\common\bin\nt; E:\Programme\Xilinx\ISE\12.3\ISE_DS\common\lib\nt; E:\Programme\WinAVR\bin; E:\Programme\WinAVR\utils\bin; E:\Programme\MiKTeX 2.8\miktex\bin; E:\WINDOWS\system32; E:\WINDOWS; E:\WINDOWS\System32\Wbem; E:\Programme\ATI Technologies\ATI.ACE\Core-Static; E:\Programme\QuickTime\QTSystem\; E:\Programme\MATLAB\R2010a\runtime\win32; E:\Programme\MATLAB\R2010a\bin; E:\Programme\TortoiseSVN\bin; D:\Programme\Pinnacle\Shared Files; D:\Programme\Pinnacle\Shared Files\Filter |
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| XILINX | E:\Programme\Xilinx\ISE\12.3\ISE_DS\ISE\ | < data not available > | < data not available > | < data not available > |
| XILINX_DSP | E:\Programme\Xilinx\ISE\12.3\ISE_DS\ISE | < data not available > | < data not available > | < data not available > |
| XILINX_EDK | E:\Programme\Xilinx\ISE\12.3\ISE_DS\EDK | < data not available > | < data not available > | < data not available > |
| XILINX_PLANAHEAD | E:\Programme\Xilinx\ISE\12.3\ISE_DS\PlanAhead | < data not available > | < data not available > | < data not available > |
| Synthesis Property Settings | |||
| Switch Name | Property Name | Value | Default Value |
| -ifn | AVR_Core.prj | ||
| -ifmt | mixed | MIXED | |
| -ofn | AVR_Core | ||
| -ofmt | NGC | NGC | |
| -p | xc3s500e-4-fg320 | ||
| -top | AVR_Core | ||
| -opt_mode | Optimization Goal | Speed | Speed |
| -opt_level | Optimization Effort | 1 | 1 |
| -iuc | Use synthesis Constraints File | NO | NO |
| -keep_hierarchy | Keep Hierarchy | No | NO |
| -netlist_hierarchy | Netlist Hierarchy | As_Optimized | As_Optimized |
| -rtlview | Generate RTL Schematic | Yes | NO |
| -glob_opt | Global Optimization Goal | AllClockNets | AllClockNets |
| -read_cores | Read Cores | YES | YES |
| -write_timing_constraints | Write Timing Constraints | NO | NO |
| -cross_clock_analysis | Cross Clock Analysis | NO | NO |
| -bus_delimiter | Bus Delimiter | <> | <> |
| -slice_utilization_ratio | Slice Utilization Ratio | 100 | 100% |
| -bram_utilization_ratio | BRAM Utilization Ratio | 100 | 100% |
| -verilog2001 | Verilog 2001 | YES | YES |
| -fsm_extract | YES | YES | |
| -fsm_encoding | Auto | AUTO | |
| -safe_implementation | No | NO | |
| -fsm_style | LUT | LUT | |
| -ram_extract | Yes | YES | |
| -ram_style | Auto | AUTO | |
| -rom_extract | Yes | YES | |
| -shreg_extract | YES | YES | |
| -rom_style | Auto | AUTO | |
| -auto_bram_packing | NO | NO | |
| -resource_sharing | YES | YES | |
| -async_to_sync | NO | NO | |
| -mult_style | Auto | AUTO | |
| -iobuf | YES | YES | |
| -max_fanout | 500 | 500 | |
| -bufg | 24 | 24 | |
| -register_duplication | YES | YES | |
| -register_balancing | No | NO | |
| -optimize_primitives | NO | NO | |
| -use_clock_enable | Yes | YES | |
| -use_sync_set | Yes | YES | |
| -use_sync_reset | Yes | YES | |
| -iob | Auto | AUTO | |
| -equivalent_register_removal | YES | YES | |
| -slice_utilization_ratio_maxmargin | 5 | 0% | |
| Operating System Information | ||||
| Operating System Information | xst | ngdbuild | map | par |
| CPU Architecture/Speed | Intel(R) Core(TM)2 Duo CPU E6750 @ 2.66GHz/2671 MHz | < data not available > | < data not available > | < data not available > |
| Host | kellerpc | < data not available > | < data not available > | < data not available > |
| OS Name | Microsoft Windows XP Professional | < data not available > | < data not available > | < data not available > |
| OS Release | Service Pack 3 (build 2600) | < data not available > | < data not available > | < data not available > |