Hallo, wer kann mir sagen, was an diesem Konstrukt falsch ist:
1 | library ieee; |
2 | use ieee.std_logic_1164.all; |
3 | |
4 | entity xyz |
5 | end xyz; |
6 | |
7 | architecture beh of xyz is |
8 | signal ls_ack, ls_sig : std_logic; |
9 | constant cGenerate : std_logic := '0'; |
10 | begin
|
11 | |
12 | g_GenTest: if cGenerate='0' generate |
13 | begin
|
14 | p_Test: process(ls_sig) |
15 | begin
|
16 | ls_ack <= ls_sig; |
17 | end process p_Test; |
18 | |
19 | |
20 | else generate --** error: near "else" expecting END |
21 | |
22 | p_Test: process(ls_sig) |
23 | begin
|
24 | ls_ack <= not ls_sig; |
25 | end process p_Test; |
26 | |
27 | end generate g_GenTest; |
28 | |
29 | end beh; |
Danke für Eure hilfe. Dietrich