entity RAM_4Bit_ is
  port (
    ADDR  : in  std_logic_vector(9 downto 0); -- Address
    DI    : in  std_logic_vector(3 downto 0); -- Data in
    DO    : out std_logic_vector(3 downto 0); -- Data out
    clk   : in std_logic;                     -- Clock
    WE    : in std_logic;                     -- Write Enable
    CE    : in std_logic                      -- Chip Enable
  );
end RAM_4Bit;
 
architecture RAM_4Bit_arch of RAM_4Bit is
  type ram_type is array (9 downto 0)
                   of std_logic_vector (3 downto 0);
  signal RAM : ram_type := (others => "0000");
begin
  process (clk)
  begin
    if (rising_edge(clk)) then
      if (CE = '1') then
        if (WE = '1') then
          RAM(to_integer(ADDR)) <= DI;
        end if;
        DO <= RAM(to_integer(ADDR));
      end if;
    end if;
  end process;
end RAM_4Bit_arch;

Loading device for application Rf_Device from file '4vlx15.nph' in environment ...
INFO:Xst:2452 - Unit <RAM_4Bit> : The small RAM <Mram_RAM> will be implemented on LUTs in order to maximize performance and save block RAM resources. If you want to force its implementation on block, use option/constraint ram_style.
    -----------------------------------------------------------------------
    | ram_type           | Distributed                         |          |
    -----------------------------------------------------------------------
    | Port A                                                              |
    |     aspect ratio   | 10-word x 4-bit                     |          |
    |     clkA           | connected to signal <clk>           | rise     |
    |     weA            | connected to signal <WE_0>          | high     |
    |     addrA          | connected to signal <ADDR>          |          |
    |     diA            | connected to signal <DI>            |          |
    |     doA            | connected to internal node          |          |
    -----------------------------------------------------------------------

type ram_type is array (9 downto 0) ...

type ram_type is array (0 to 2**ADDR'length-1) ...

> type ram_type is array (0 to 2**ADDR'length-1) ...
> 

component RAMB16_S1_S36 
  port (
  DIA     : in std_logic_vector (0 downto 0);
  ADDRA   : in std_logic_vector (13 downto 0);
  ENA     : in std_logic;
  WEA     : in std_logic;
  SSRA    : in std_logic;
  CLKA    : in std_logic;
  DOA     : out std_logic_vector (0 downto 0);

  DIB     : in std_logic_vector (31 downto 0);
  DIPB    : in std_logic_vector (3 downto 0);
  ADDRB   : in std_logic_vector (8 downto 0);
  ENB     : in std_logic;
  WEB     : in std_logic;
  SSRB    : in std_logic;
  CLKB    : in std_logic;
  DOB     : out std_logic_vector (31 downto 0);
  DOPB    : out std_logic_vector (3 downto 0)  
  ); 
end component;

U_RAMB16_S1_S36: RAMB16_S1_S36
  port map (
  DIA     => X, -- insert 1 bit data in bus (<0 downto 0>)
  ADDRA   => Y, -- insert 14 bits address bus
  ENA     => Z, -- insert enable signal
  ...

  port map (
  DIA     => datain,  -- insert 1 bit data in bus (<0 downto 0>)
  ADDRA   => addrin,  -- insert 14 bits address bus
  ENA     => '1',     -- insert enable signal / immer enabled
  WEA     => write,   -- insert write enable signal 
  SSRA    => '0',     -- insert set/reset signal
  CLKA    => clkin,   -- insert clock signal
  DOA     => open,    -- insert 1 bit data out bus (<0 downto 0>)
--
  DIB     => (others=>'0'), -- insert 32 bits data in bus (<31 downto 0>)
  DIPB    => (others=>'0'), -- insert 4 bits parity data in bus (or <35 downto 32>)
  ADDRB   => addrout, -- insert 9 bits address bus
  ENB     => '1',     -- insert enable signal / immer enabled
  WEB     => '0',     -- insert write enable signal / nur lesen
  SSRB    => '0',     -- insert set/reset signal
  CLKB    => clkout,  -- insert clock signal
  DOB     => dataout, -- insert 32 bits data out bus (<31 downto 0>)
  DOPB    => open     -- insert 4 bits parity data out bus (or <35 downto 32>)
  );

--  <-----Cut code below this line and paste into the architecture body---->
   -- RAMB16_S1_S18: Virtex-II/II-Pro, Spartan-3/3E 16k/1k x 1/16 + 0/2 Parity bits Dual-Port RAM
   -- Xilinx HDL Language Template, version 9.2.1i
   RAMB16_S1_S18_inst : RAMB16_S1_S18
   generic map (
      INIT_A => "0", --  Value of output RAM registers on Port A at startup
      INIT_B => X"00000", --  Value of output RAM registers on Port B at startup
      SRVAL_A => "0", --  Port A ouput value upon SSR assertion
      SRVAL_B => X"00000", --  Port B ouput value upon SSR assertion
      WRITE_MODE_A => "WRITE_FIRST", --  WRITE_FIRST, READ_FIRST or NO_CHANGE
      WRITE_MODE_B => "WRITE_FIRST", --  WRITE_FIRST, READ_FIRST or NO_CHANGE
      SIM_COLLISION_CHECK => "ALL", -- "NONE", "WARNING", "GENERATE_X_ONLY", "ALL" 
      -- The following INIT_xx declarations specify the initial contents of the RAM
      -- Port A Address 0 to 4095, Port B Address 0 to 255
      INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
      ...
      INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
      -- Port A Address 4096 to 8191, Port B Address 256 to 511
      INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
      ...
      INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
      -- Port A Address 8192 to 12287, Port B Address 512 to 767
      INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
      ...
      INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
      -- Port A Address 12288 to 16383, Port B Address 768 to 1023
      INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
      ...
      INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
      -- The next set of INITP_xx are for the parity bits
      -- Port B Address 0 to 255
      INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
      ...
      INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000")
   port map (
      DOA => DOA,       -- Port A 1-bit Data Output
      DOB => DOB,       -- Port B 16-bit Data Output
      DOPB => DOPB,     -- Port B 2-bit Parity Output
      ADDRA => ADDRA,   -- Port A 14-bit Address Input
      ADDRB => ADDRB,   -- Port B 10-bit Address Input
      CLKA => CLKA,     -- Port A Clock
      CLKB => CLKB,     -- Port B Clock
      DIA => DIA,       -- Port A 1-bit Data Input
      DIB => DIB,       -- Port B 16-bit Data Input
      DIPB => DIPB,     -- Port-B 2-bit parity Input
      ENA => ENA,       -- Port A RAM Enable Input
      ENB => ENB,       -- PortB RAM Enable Input
      SSRA => SSRA,     -- Port A Synchronous Set/Reset Input
      SSRB => SSRB,     -- Port B Synchronous Set/Reset Input
      WEA => WEA,       -- Port A Write Enable Input
      WEB => WEB        -- Port B Write Enable Input
   );
   -- End of RAMB16_S1_S18_inst instantiation