1 | * SIMPLE UART "ECHO" CODE
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2 |
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3 | * Register initialization values before execution:
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4 | *
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5 | * PC=00030300 SR=2700
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6 | * USP=00080000 *ISP=00004000 (Stack pointers not used)
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7 | *
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8 | * D1 = SCCE3 holding register
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9 | * D3 = count of characters received
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10 | * D4 = count of characters transmitted
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11 | * D5 = count of BSY conditions occuring (no receive buffers available)
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12 | * D6 = 1 or greater, if character(s) waiting to be transmitted, 0 otherwise
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13 | * A0 = current Rx BD pointer
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14 | * A1 = current "next TX byte" to send pointer
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15 | * A2 = current Tx BD pointer
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16 | * A3 = temp
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17 |
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18 | * SCC3 Tx Buffer Descriptors initialization:
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19 | * 00700640 5000 0000 0003 0000
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20 | * 00700648 7000 0000 0003 0001 (wrap bit set)
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21 |
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22 | * SCC3 Rx Buffer Descriptors initialization:
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23 | * 00700600 d000 0000 0003 0002
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24 | * 00700608 f000 0000 0003 0003 (wrap bit set)
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25 |
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26 | BAR EQU $0F2
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27 | GIMR EQU $700812
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28 | IPR EQU $700814
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29 | IMR EQU $700816
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30 | ISR EQU $700818
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31 | PACNT EQU $70081e
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32 | SIMODE EQU $7008b4
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33 | SCON3 EQU $7008a2
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34 | SCM3 EQU $7008a4
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35 | SCCE3 EQU $7008a8
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36 | SCCM3 EQU $7008aa
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37 |
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38 | * SCC3 initialization code:
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39 |
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40 | ORG $30300
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41 |
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42 | MOVE.W #$700,BAR ; BAR = 0700
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43 | * Base Address = $700000, so ALL 68302 on-chip peripherals begin at
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44 | * address $700xxx.
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45 |
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46 | MOVE.W #$00A0,GIMR ; GIMR = 00a0
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47 | MOVE.W #$FFFF,IPR ; clear IPR
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48 | MOVE.L #$30500,$2a0 ; SCC3 vector initialization
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49 |
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50 | MOVE.W #$0300,PACNT ; PACNT = 0300
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51 | * Causes the SCC3 TXD3 and RXD3 pins to be enabled. TCLK3 and RCLK3
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52 | * pins are left as parallel I/O pins.
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53 |
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54 | MOVE.W #$0,SIMODE ; SIMODE = 0000 (its reset value)
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55 | * SCC3 is set up for NMSI (i.e. modem) operation. No multiplexed
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56 | * modes are used on the other SCCs.
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57 |
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58 | MOVE.W #$00d8,SCON3 ; SCON3 = 00d8 for ~9600 baud at 16.67 MHz
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59 | * Baud Rate generator is used for transmit and receive. Rate is 9556bps.
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60 |
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61 | MOVE.W #$171,SCM3 ; SCM3 = 0171
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62 | * No parity. Normal UART operation. 8-bit characters. 2 Stop bits.
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63 | * The CD* and CTS* lines not used to enable reception and transmission,
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64 | * but do cause a status change in the SCC3 Event register.
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65 |
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66 | MOVE.L #$50000000,$700640 ; Set up Tx BD 0 Status and Count
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67 | MOVE.L #$30000,$700644 ; Set up Tx BD 0 Buffer Address
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68 | MOVE.L #$70000000,$700648 ; Set up Tx BD 1 Status and Count
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69 | MOVE.L #$30001,$70064c ; Set up Tx BD 1 Buffer Address
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70 | * Set up 2 Tx BDs
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71 |
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72 | MOVE.L #$d0000000,$700600 ; Set up Rx BD 0 Status and Count
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73 | MOVE.L #$30002,$700604 ; Set up Rx BD 0 Buffer Address
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74 | MOVE.L #$f0000000,$700608 ; Set up Rx BD 1 Status and Count
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75 | MOVE.L #$30003,$70060c ; Set up Rx BD 1 Buffer Address
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76 | * Set up 2 Rx BDs
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77 |
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78 | MOVE.W #$0,$700680 ; clear RFCR/TFCR (Function code setup)
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79 | * Must be initialized to a value other than 7, or won't work with chip selects
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80 |
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81 | MOVE.W #$1,$700682 ; MRBLR = 0001 (one-byte receive buffers)
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82 | * This combined with the "I" bit set in the Rx BD, gives interrupts on each
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83 | * character received.
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84 |
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85 | MOVE.W #$4,$70069c ; MAX_IDL don't care since MRBLR = 1.
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86 | * Normally set to a small value, it closes a receive buffer if a certain
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87 | * number of idles are received without a new character. Note that 0 is the
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88 | * maximum value. In this case the buffer will always be closed after 1
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89 | * character, so MAX_IDL is a don't care.
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90 |
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91 | MOVE.W #$1,$7006A0 ; BRKCR = 1. Only one break char. sent if
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92 | * STOP TRANSMIT command executed. The STOP TRANSMIT command is not used in
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93 | * this code.
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94 |
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95 | MOVE.W #$0,$7006A2 ; PAREC = 0000
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96 | MOVE.W #$0,$7006A4 ; FRMEC = 0000
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97 | MOVE.W #$0,$7006A6 ; NOSEC = 0000
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98 | MOVE.W #$0,$7006A8 ; BRKEC = 0000
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99 | * Initialize counters to zero
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100 |
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101 | MOVE.W #$0,$7006aa ; UADDR1 = 0000
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102 | MOVE.W #$0,$7006ac ; UADDR2 = 0000
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103 | * UART Address characters not used in normal operation.
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104 |
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105 | MOVE.W #$8000,$7006B0 ; CHARACTER1 = 8000
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106 | * No control characters are initialized to cause special interrupts.
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107 | * The flow-control facility (XON-XOFF) is not used.
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108 |
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109 | MOVE.B #$FF,SCCE3 ; clear SCCE3
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110 | MOVE.B #$15,SCCM3 ; SCCM3 = 15
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111 | * Interrupts in SCCM3 are allowed only for BRK (break character
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112 | * received), BSY (no receive buffer available), and RX (buffer
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113 | * received). Note that buffers are 1 character in this application.
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114 |
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115 | MOVE.W #$0100,IMR ; IMR = 0100. Allow SCC3 interrupts only.
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116 |
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117 | MOVE.W #$17d,SCM3 ; SCM3 = 017d
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118 | * Set ENR and ENT bits in SCM3.
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119 |
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120 | CLR.L D0 ; clear all used data registers
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121 | CLR.L D1
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122 | CLR.L D3
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123 | CLR.L D4
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124 | CLR.L D5
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125 | CLR.L D6
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126 |
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127 | MOVEA.L #$700600,A0 ; Load A0 as current Rx BD pointer
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128 | MOVEA.L #$30002,A1 ; Load A1 as current "next Tx Byte" ptr
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129 | MOVEA.L #$700640,A2 ; Load A2 as current Tx BD pointer
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130 |
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131 | MOVE.W #$2000,SR ; Enable interrupts. Stay in spvr mode.
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132 |
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133 | ****************************************************************************
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134 | * Transmit Code
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135 |
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136 | * OUTERLOOP:
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137 | OUTLOOP CMPI.B #$0,D6 ; Something to send (is D6>=1?)
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138 | BEQ.B OUTLOOP ; Stay in outerloop if 0
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139 | SUBQ.B #$1,D6 ; Decrement send status by 1 (0=empty)
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140 |
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141 | * INNERLOOP:
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142 | INLOOP BTST.B #$0F,(A2) ; Test Ready bit of Tx BD
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143 | BNE.B INLOOP ; Fall thru if 0, else wait in innerloop
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144 |
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145 | * The following sets up and sends out the transmit buffer
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146 | ADDQ.W #$1,D4 ; Increment number of chars transmitted
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147 | MOVEA.L A2,A3 ; A3 will be used to find Tx data buffer
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148 | ADDQ.W #$4,A3 ; Inc A3 to point to Tx data pointer
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149 | MOVEA.L (A3),A3 ; A3 now points to Tx Data buffer
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150 | MOVE.B (A1),(A3) ; Move char from Rx Buffer to Tx Buffer
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151 | ADDQ.W #2,A2 ; Increment A2 to point to byte count
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152 | MOVE.W #$1,(A2) ; Set Tx BD Byte count to 1
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153 | SUBQ.W #2,A2 ; A2 now points to beginning of Tx BD
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154 | BSET.B #$07,(A2) ; Set Ready bit of Tx BD
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155 | * The Tx BD send data status is not checked since the only one is CTS* lost,
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156 | * which is not applicable, since CTS is ignored in this application.
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157 |
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158 | * The following updates A2 to point to the next Tx BD
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159 | BTST.B #$05,(A2) ; test Wrap bit
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160 | BNE.B REINIT2 ; If set, reinit A2 to 700640
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161 | ADDA.W #$08,A2 ; else inc A2 by 8 to next Tx BD
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162 | BRA.B CONT ; Jump to Continue on
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163 | REINIT2 MOVEA.L #$700640,A2 ; Reinitialize A2
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164 |
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165 | * Determine what the next byte to "echo" will be and then go to OUTERLOOP
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166 | CONT ADDQ.W #$1,A1 ; Increment A1 to next byte to send
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167 | CMPA.L #$30004,A1 ; Is A1 = 30004? ***
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168 | BEQ.B NEWA1 ; If so, go to NEWA1
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169 | BRA.B OUTLOOP ; Jump back to outerloop and wait
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170 | NEWA1 SUBQ.W #$02,A1 ; Set A1 back to 30002 ***
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171 | BRA.B OUTLOOP ; Jump back to outerloop and wait
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172 | * The two lines with *** above are dependent on the number of Rx BDs used.
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173 | * If the number is increased, these values should be increased by the same
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174 | * amount. These are the only lines dependent on the Rx BD or Tx BD setup.
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175 |
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176 | ******************************************************************************
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177 | * SCC3 interrupt routine:
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178 |
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179 | ORG $30500
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180 |
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181 | CLR.L D1 ; clear D1
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182 | MOVE.B SCCE3,D1 ; Move SCCE3 status to D1
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183 | MOVE.B #$15,SCCE3 ; Clear only BRK, BSY and RX in SCCE3.
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184 |
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185 | BTST.B #$2,D1 ; Is BSY set?
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186 | BNE.B BUSY ; Jump to BUSY handler if set
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187 |
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188 | * Test Break:
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189 | BRKTEST BTST.B #$4,D1 ; Is BRK set?
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190 | BNE.B BREAK ; Jump to BREAK handler if set
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191 |
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192 | * Test Receive:
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193 | RECTEST BTST.B #$0,D1 ; Is RX set?
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194 | BNE.B RECEIVE ; Jump to RECEIVE handler if set
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195 | JMP ALMDONE ; Jump to About Done (impossible)
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196 |
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197 | * Busy handler:
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198 | BUSY ADDQ.B #1,D5 ; Inc Busy counter (no receive buffers)
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199 | BSET.B #$F,(A0) ; set Empty bit of current Rx BD
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200 | JMP BRKTEST ; Jump to test for BREAK
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201 |
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202 | * Break handler:
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203 | BREAK NOP ; This code ignores received breaks
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204 | * The UART BRKEC will record the number of breaks received
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205 | JMP RECTEST ; Jump to test for RECEIVE
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206 |
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207 | * Receive handler:
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208 | RECEIVE ADDQ.W #1,D3 ; Increment number of chars received
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209 | ADDQ.B #1,D6 ; D6 inc by 1 (character ready to send)
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210 |
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211 | ADDQ.W #1,A0 ; Inc A0 to point to Rx BD byte status
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212 | CMPI.B #$0,(A0) ; Does status = 00?
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213 | BNE.B BSTAT ; Jump to Bad Status if not 00
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214 | INCPTR SUBQ.W #1,A0 ; Dec A0 to point to beginning of Rx BD
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215 | ANDI.W #$FF00,(A0) ; Clear out Rx BD status
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216 | BSET.B #$07,(A0) ; Set Empty bit of Rx BD
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217 | BTST.B #$05,(A0) ; test Wrap bit
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218 | BNE.B REINIT0 ; If set, reinit A0 to 700600
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219 | ADDA.W #$08,A0 ; else inc A0 by 8 to next Rx BD
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220 | BRA.B ALMDONE ; Jump to Almost Done
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221 | REINIT0 MOVEA.L #$700600,A0 ; Reinitialize A0
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222 | BRA.B ALMDONE ; Jump to almost Done
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223 |
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224 | * Bad Status:
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225 | BSTAT NOP ; Bad status handler would go here
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226 | * Note that the UART FRMEC, NOSEC, and PAREC counters record bad status.
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227 | BRA.B INCPTR ; Jump back to Receive handler
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228 |
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229 | * Almost Done:
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230 | ALMDONE MOVE.W #$0100,ISR ; Clear SCC3 bit in the ISR
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231 | RTE ; end of interrupt handler
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232 | END
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