mal wieder: bad synchronous description.

[Tim (Gast)]

Hallo liebe Experten!

Ich bin Neuling in VHDL, würde aber gerne wissen, warum ich die 
Fehlermeldung
"Signal sreg_data_in<0> cannot be synthesized, bad synchronous 
description.
erhalte."
Könnt Ihr mir bitte bei dem SPI-Interface weiterhelfen? Die Daten kommen 
parallel und sollen per Load zum Senden losgeschickt werden.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity spi_exchange_unit is
   generic( --
            -- data width
            WIDTH : integer := 8
   );
   port( Slow_clk : in STD_LOGIC;
         Data_tx  : in STD_LOGIC_VECTOR (7 downto 0);
         Data_rx  : out STD_LOGIC_VECTOR (7 downto 0);
         Load     : in STD_LOGIC;
         Done     : out STD_LOGIC;
         SCK      : out STD_LOGIC;
         MOSI     : out STD_LOGIC;
         MISO     : in STD_LOGIC);
end spi_exchange_unit;

architecture Behavioral of spi_exchange_unit is

   signal sreg_data_in  : std_logic_vector(7 downto 0) := (others => '0');
   signal sreg_data_out : std_logic_vector(7 downto 0) := (others => '0');
   signal databit_in    : integer range 0 to 8 := 0;
   signal databit_out   : integer range 0 to 7 := 0;

begin

   SCK <= Slow_clk;

   exchange_data : process(Slow_clk, Load, Data_tx, sreg_data_out, sreg_data_in, databit_out, databit_in)
      begin
         if Load = '1' then
            Done <= '0';
            sreg_data_out <= Data_tx;
            databit_out <= WIDTH-1;
            databit_in <= WIDTH;
            MOSI <= Data_tx(WIDTH-1);
         end if;
         if falling_edge(Slow_clk) then
            if databit_out > 0 then
               MOSI <= sreg_data_out(databit_out-1);
               databit_out <= databit_out - 1;
            else
               Done <= '1';
               MOSI <= '0';
               Data_rx <= sreg_data_in(WIDTH-1 downto 0);
            end if;
         elsif rising_edge(Slow_clk) then
            if databit_in > 0 then
               sreg_data_in(databit_in-1) <= MISO;
               databit_in <= databit_in - 1;
            end if;
         end if;
      end process exchange_data;

end Behavioral;

Liebe Grüße
Tim

[Tim (Gast)]

Problem gelöst. Hier auch für alle anderen:

entity spi_exchange_unit is
   generic( --
            -- data width
            WIDTH : integer := 8
   );
   port( Slow_clk : in STD_LOGIC;
         Data_tx  : in STD_LOGIC_VECTOR (7 downto 0);
         Data_rx  : out STD_LOGIC_VECTOR (7 downto 0);
         Load     : in STD_LOGIC;
         Done     : out STD_LOGIC;
         SCK      : out STD_LOGIC;
         MOSI     : out STD_LOGIC;
         MISO     : in STD_LOGIC
   );
end spi_exchange_unit;

architecture Behavioral of spi_exchange_unit is

   signal sreg_data_in  : std_logic_vector(7 downto 0) := (others => '0');
   signal sreg_data_out : std_logic_vector(7 downto 0) := (others => '0');
   signal databit_in    : integer range 0 to 8 := 0;
   signal databit_out   : integer range 0 to 8 := 0;

begin

   SCK <= Slow_clk;
   
   receive_data : process(Slow_clk, Load, sreg_data_in, databit_in)
   begin
      if Load = '1' then
         databit_in <= WIDTH;
      elsif rising_edge(Slow_clk) then
         if databit_in > 0 then
            sreg_data_in(databit_in-1) <= MISO;
            databit_in <= databit_in - 1;
         end if;
      end if;
   end process receive_data;

   send_data : process(Slow_clk, Load, Data_tx, sreg_data_out, databit_out)
   begin
      if Load = '1' then
         Done <= '0';
         sreg_data_out <= Data_tx;
         databit_out <= WIDTH-1;
         MOSI <= Data_tx(WIDTH-1);
      elsif falling_edge(Slow_clk) then
         if databit_out > 0 then
            MOSI <= sreg_data_out(databit_out-1);
            databit_out <= databit_out - 1;
         else
            Done <= '1';
            MOSI <= '0';
            Data_rx <= sreg_data_in(WIDTH-1 downto 0);
         end if;
      end if;
   end process send_data;

end Behavioral;

Gruß

[Lothar M. (Firma: Titel) (lkmiller) (Moderator)]

>> Signal ... cannot be synthesized, bad synchronous description.
> Hier auch für alle anderen:
Falls jemand mal wissen will, woran es gelegen hat...

         if falling_edge(Slow_clk) then
          :
         elsif rising_edge(Slow_clk) then
          :
         end if;

So ein Flipflop, das auf eine steigende und eine fallende Flanke 
reagieren kann, gibt es bestenfalls in den IO-Zellen (als DDR-FF).

> Problem gelöst.
Aber nur unsauber:
Mit dem asynchronen Reset kann eine Übertragung jederzeit undefiniert 
terminiert werden.

Besser wäre das SPI-Interface über ein Schieberegister statt mit einem 
Multiplexer realisiert worden. Denn SPI ist eigentlich nur ein 
gekoppeltes Schieberegister... :-/