Hallo,
ich würde gerne wissen ob man grundsätzlich nur Taktflankenauswertungen
auf Clocks vornehmen sollte, oder ob dies auch theoretisch auf bspw.
Buttons angewendet werden kann.
Ich hatte einen kleinen Zähler aufgesetzt der auf die steigende Flanke
des Buttons das Ergebnis erhöht, jedoch bekomme ich, abhängig von den
ausgewählten Buttons, warnings oder errors.
Stellt sich mir halt die Frage ob man dies prinzipiell sein lassen
sollte oder ob dies andere Gründe hat.
1 | library IEEE;
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2 | use IEEE.STD_LOGIC_1164.ALL;
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3 | use IEEE.NUMERIC_STD.ALL;
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4 |
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5 | entity toplevel is
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6 | port( RST : in std_logic;
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7 | BTN2 : in std_logic;
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8 | LED1 : out std_logic;
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9 | LED2 : out std_logic;
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10 | LED3 : out std_logic;
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11 | LED4 : out std_logic);
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12 | end toplevel;
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13 |
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14 | architecture Behavioral of toplevel is
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15 | signal LED_TMP : unsigned(3 downto 0);
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16 |
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17 | begin
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18 |
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19 | BTN_CNT_UP : process(BTN2, RST)
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20 | begin
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21 | if(RST = '1') then
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22 | LED_TMP <= "0000";
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23 | elsif(BTN2'event and BTN2 = '1') then
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24 | LED_TMP <= LED_TMP + 1;
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25 | end if;
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26 | end process;
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27 |
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28 |
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29 | LED1 <= LED_TMP(0);
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30 | LED2 <= LED_TMP(1);
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31 | LED3 <= LED_TMP(2);
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32 | LED4 <= LED_TMP(3);
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33 |
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34 | end Behavioral;
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Bei Nutzung von BTN1:
Warning:Place:619 - This design is using a Side-BUFG site due to
placement constraints on a BUFG, DCM, clock IOB or the
loads of these components. It is recommended that Top and Bottom BUFG
sites be used instead of Side-BUFG sites
whenever possible because they can reach every clock region on the
device. Side-BUFG sites can reach only clock
regions on the same side of the device and also preclude the use of
certain Top and Bottom BUFGs in the same clock
region.
Bei Nutzung von BTN2:
(Zwar kann man den Error mit NET "BTN2" CLOCK_DEDICATED_ROUTE = FALSE;
beseitigen, jedoch schränke ich mich dann anderweitig ein)
Error: Place:1018 - A clock IOB / clock component pair have been found
that are not placed at an optimal clock IOB /
clock site pair. The clock component <BTN2_BUFGP/BUFG> is placed at
site <BUFGMUX_X1Y10>. The IO component <BTN2> is
placed at site <PAD287>. This will not allow the use of the fast
path between the IO and the Clock buffer. If this
sub optimal condition is acceptable for this design, you may use the
CLOCK_DEDICATED_ROUTE constraint in the .ucf
file to demote this message to a WARNING and allow your design to
continue. However, the use of this override is
highly discouraged as it may lead to very poor timing results. It is
recommended that this error condition be
corrected in the design. A list of all the COMP.PINs used in this
clock placement rule is listed below. These
examples can be used directly in the .ucf file to override this clock
rule.
< NET "BTN2" CLOCK_DEDICATED_ROUTE = FALSE; >