library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.Numeric_std.ALL;

entity Sinc_filt is
  generic ( 
         DECIMATOR_M_BIT_SIZE   : natural := 8); -- M = 2^DECIMATOR_M_BIT_SIZE
    Port ( Mclk : in  STD_LOGIC;
           Mdata : in  STD_LOGIC;
           rst : in  STD_LOGIC;
           DataRate_clk : out  STD_LOGIC; -- in fifo abspeichern 
           DataOut : out  STD_LOGIC_VECTOR (15 downto 0));
end Sinc_filt;

architecture Behavioral of Sinc_filt is

  constant DATA_BIT_SIZE : natural := 3*DECIMATOR_M_BIT_SIZE + 1; -- intern DatenBus Sinc3

  ----------------------------------------------------------------------------------
  -- signal
  ----------------------------------------------------------------------------------
    
  -- integrator @ Mclk
  signal acc1    : signed (DATA_BIT_SIZE - 1 downto 0) := (others => '0');
  signal acc2    : signed (DATA_BIT_SIZE - 1 downto 0) := (others => '0');
  signal acc3    : signed (DATA_BIT_SIZE - 1 downto 0) := (others => '0');
  
  -- diffirentiator @ Mclk/DECIMATOR_M
  signal diff_clk : std_logic := '0';

  signal diff1    : signed (DATA_BIT_SIZE - 1 downto 0) := (others => '0');
  signal diff2    : signed (DATA_BIT_SIZE - 1 downto 0) := (others => '0');
  signal diff3    : signed (DATA_BIT_SIZE - 1 downto 0) := (others => '0');
  signal acc3_d   : signed (DATA_BIT_SIZE - 1 downto 0) := (others => '0');
  signal diff1_d  : signed (DATA_BIT_SIZE - 1 downto 0) := (others => '0');
  signal diff2_d  : signed (DATA_BIT_SIZE - 1 downto 0) := (others => '0');
  
  -- clk divider ->> Mclk/DECIMATOR_M
  signal clk_div_cnt : std_logic_vector(DECIMATOR_M_BIT_SIZE-1 downto 0) := (others => '0');
  
begin
  
  ----------------------------------------------------------------------------------
  -- Integrator @ Mclk
  ----------------------------------------------------------------------------------
  Integ_pro: process
  begin
    wait until rising_edge(Mclk); -- falling Mclk ->> data valid
      
    if rst = '1' then
      acc1 <= (others => '0');
      acc2 <= (others => '0');
      acc3 <= (others => '0');
    else
      if Mdata = '1' then
        acc1 <= acc1 + x"1";
      end if;
      acc2 <= acc2 + acc1;
      acc3 <= acc3 + acc2;
    end if;
  end process Integ_pro;

  ----------------------------------------------------------------------------------
  -- clk divider @ Mclk --> Mclk/DECIMATOR_M
  ----------------------------------------------------------------------------------
  clk_div_pro: process
  begin
    wait until rising_edge(Mclk);
    if rst = '1' then
      clk_div_cnt <= (others => '0');
    else
      clk_div_cnt <= std_logic_vector(unsigned(clk_div_cnt) + x"1");
    end if;
  end process clk_div_pro;
  
  -- wired
  diff_clk <= clk_div_cnt(DECIMATOR_M_BIT_SIZE-1);  -- MSB
  DataRate_clk <= diff_clk; 
  
  ----------------------------------------------------------------------------------
  -- differenciator @ falling diff_clk 
  ----------------------------------------------------------------------------------
  Diff_pro: process
  begin
    wait until falling_edge(diff_clk); -- Falling Edge!
      
    if rst = '1' then
      diff1 <= (others => '0');
      diff2 <= (others => '0');
      diff3 <= (others => '0');
      acc3_d <= (others => '0');
      diff1_d <= (others => '0');
      diff2_d <= (others => '0');
    else
      diff1 <= acc3  - acc3_d;
      diff2 <= diff1 - diff1_d;
      diff3 <= diff2 - diff2_d;
      
      acc3_d  <= acc3;
      diff1_d <= diff1;
      diff2_d <= diff2;
    end if;
  end process Diff_pro;


  ----------------------------------------------------------------------------------
  -- 16- bit DataOutput 
  ----------------------------------------------------------------------------------

  DataOut <= std_logic_vector(diff3(DATA_BIT_SIZE-1 downto DATA_BIT_SIZE-16)); -- 16-Bit DataOut

end Behavioral;