library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;

entity vga_control is
port (
reset, taster           : in std_logic;
clk                     : in std_logic; 

VGA_CLK,                                    -- Should be 25.125 MHz VGA_CLK,  Dot clock to DAC
VGA_HS,                                     -- Active Low Horizontal Sync
VGA_VS,                                     -- Active Low Vertical Sync
VGA_BLANK,                                   -- Active Low DAC blanking control
VGA_SYNC         : out std_logic;                -- Active Low DAC Sync on Green
VGA_R, VGA_G, VGA_B   : out std_logic_vector(7 downto 0);
ledtest1, ledtest2, ledtest3           : out std_logic := '0'
);

end vga_control;

architecture rtl of vga_control is

-- Video parameters

constant HTOTAL           : integer := 800;
constant HSYNC           : integer := 96;
constant HBACK_PORCH       : integer := 48; 
constant HACTIVE           : integer := 640;
constant HFRONT_PORCH       : integer := 16;
constant VTOTAL           : integer := 525;
constant VSYNC           : integer := 2;
constant VBACK_PORCH       : integer := 33;
constant VACTIVE           : integer := 480;
constant VFRONT_PORCH       : integer := 10;
constant RECTANGLE_HSTART     : integer := 100;
constant RECTANGLE_HEND     : integer := 540;
constant RECTANGLE_VSTART     : integer := 100;
constant RECTANGLE_VEND     : integer := 380;

signal Hcount             : std_logic_vector(9 downto 0):= "0000000000"; -- Horizontal position (0 - 800)
signal Vcount             : std_logic_vector(9 downto 0):= "0000000000";  -- Vertical position (0 - 524)
signal EndOfLine, EndOfField   : std_logic :='0';
signal vga_hblank, vga_hsync,
vga_vblank, vga_vsync       : std_logic;                     -- Sync. signals

signal rectangle_h, rectangle_v, rectangle : std_logic;        -- rectangle area

begin

test : process (clk)
begin

  if taster= '1' then
    ledtest1<='0';
  else
    ledtest1<='1';
  end if;

end process test;


 
HCounter : process (clk)
begin

  if reset = '0' then
    Hcount <= (others=> '0');
    ledtest2<='1';
    elsif  (clk'event and clk = '1') then
     ledtest2<='0';
   if EndOfLine = '1' then
    Hcount <= (others=> '0');
  else
    Hcount <= Hcount + 1;
  
  end if; 
  end if;

end process;


VCounter: process (clk)
begin

  if reset = '0' then
    Vcount <= (others=> '0');

  elsif (clk'event and clk = '1') then
      if EndOfLine = '1' then
      if  EndOfField = '1' then
        Vcount <= (others=> '0');
      
      else
        Vcount <= Vcount + 1;
      end if;
      end if;
  end if;
end process VCounter;


 HSyncGen : process (clk)
begin
  if reset = '1' then
    vga_hsync <= '1';
  elsif clk'event and clk = '1' then
    if EndOfLine = '1' then
      vga_hsync <= '1';
    elsif Hcount = HSYNC - 1 then 
        vga_hsync <= '0';
      end if;
  end if;
end process HSyncGen;

HBlankGen : process (clk)
begin

  if reset='1' then 
  vga_hblank <= '1';

  elsif clk'event and clk='1' then
  
      if Hcount = HSYNC + HBACK_PORCH then
        vga_hblank <= '0';
      elsif Hcount = HSYNC + HBACK_PORCH + HACTIVE then
          vga_hblank <= '1';
      end if;
      
  end if;
end process HBlankGen;



VSyncGen : process (clk)
begin

  if reset='1' then
    vga_vsync <= '1';
  elsif clk'event and clk = '1' then
    if EndOfLine ='1' then
    if EndOfField = '1' then
      vga_vsync <= '1';
  elsif Vcount = VSYNC - 1 then
      vga_vsync <= '0';
    end if;
    end if;
  end if;
end process VSyncGen;


VBlankGen : process (clk)
begin

  if reset = '1' then
    vga_vblank <= '1';
  elsif clk'event and clk = '1' then
    if EndOfLine = '1' then
    if Vcount = VSYNC + VBACK_PORCH - 1 then
      vga_vblank <= '0';
    elsif Vcount = VSYNC + VBACK_PORCH + VACTIVE - 1 then
        vga_vblank <= '1';
    end if;
    end if;
  end if;
end process VBlankGen;


RectangleHGen : process (clk)
begin

  if reset = '1' then
    rectangle_h <= '1';
  elsif clk'event and clk = '1' then
    if Hcount = HSYNC + HBACK_PORCH + RECTANGLE_HSTART then
      rectangle_h <= '1';
    elsif Hcount = HSYNC + HBACK_PORCH + RECTANGLE_HEND then
        rectangle_h <= '0';
    end if;
  end if;
end process RectangleHGen;


RectangleVGen : process (clk)
begin
  if reset = '1' then
  rectangle_v <= '0';
  elsif clk'event and clk = '1' then
    if EndOfLine = '1' then
    if Vcount = VSYNC + VBACK_PORCH - 1 + RECTANGLE_VSTART then
      rectangle_v <= '1';
  elsif Vcount = VSYNC + VBACK_PORCH - 1 + RECTANGLE_VEND then
      rectangle_v <= '0';

    end if;
    end if;
  end if;
end process RectangleVGen;

rectangle <= rectangle_h and rectangle_v;



VideoOut: process (clk)
begin
  
  if reset = '1' then
    VGA_R <= "00000000";
    VGA_G <= "00000000";
    VGA_B <= "00000000";
  elsif clk'event and clk = '1' then

  if rectangle = '1' then
    VGA_R <= "11111111";
    VGA_G <= "11111111";
    VGA_B <= "11111111";
  elsif vga_hblank = '0' and vga_vblank ='0' then
      VGA_R <= "00000000";
      VGA_G <= "00000000";
      VGA_B <= "11111111";
  else
    VGA_R <= "00000000";
    VGA_G <= "00000000";
    VGA_B <= "00000000";
  end if;
  end if;
end process VideoOut;


vga_clk_gen : PROCESS(clk)--devides 50MHz clock in 2, making it a 25MHz clock
       VARIABLE count : INTEGER := 0;
    BEGIN

       IF rising_edge(clk) THEN
          IF count = 0 THEN
              VGA_CLK <= '1';   --1 period of 50MHz high
              count := 1;
          ELSIF count = 1 THEN
              VGA_CLK <= '0';    
              count := 0;
       END IF; 
     END IF;
    END PROCESS vga_clk_gen;



VGA_HS <= not vga_hsync;
VGA_VS <= not vga_vsync;
VGA_SYNC <='0';
VGA_BLANK <= not (vga_hsync or vga_vsync);

end rtl;