1 | entity Main is
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2 | Port (
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3 | SYS_clk : in STD_LOGIC;
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4 | Reset : in STD_LOGIC;
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5 | -- UART_Control
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6 | UART_SEND_data : out STD_LOGIC_VECTOR (63 downto 0); -- zu sendende Daten
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7 | UART_SEND_data_en : out STD_LOGIC; -- 1 -> Send_Data sollen gesendet werden
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8 | UART_SEND_ready : in std_logic; -- 1 -> bereit zum senden
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9 | -- QSPI-BUFF
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10 | BUFF_RD_sampled_data : out STD_LOGIC;
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11 | BUFF_SAMPLED_data_out : in STD_LOGIC_VECTOR(63 downto 0);
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12 | BUFF_FIFO_empty : in STD_LOGIC;
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13 | -- DDR_2_RAM
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14 | DDR_R_w : out STD_LOGIC;
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15 | DDR_R_w_en : out STD_LOGIC;
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16 | DDR_Address : out STD_LOGIC_VECTOR(23 downto 0);
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17 | DDR_DDR2_rdy : in STD_LOGIC;
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18 | DDR_DATA_out : in STD_LOGIC_VECTOR(63 downto 0);
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19 | DDR_DATA_in : out STD_LOGIC_VECTOR(63 downto 0);
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20 | DDR_empty : out STD_LOGIC;
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21 |
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22 | deb_ADDR_rd : out STD_LOGIC_VECTOR(23 downto 0);
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23 | deb_ADDR_wr : out STD_LOGIC_VECTOR(23 downto 0);
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24 | deb_ueberlauf: out STD_LOGIC;
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25 | deb_WR_err : out STD_LOGIC;
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26 | deb_RD_err : out STD_LOGIC;
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27 | deb_state : out STD_LOGIC_VECTOR(2 downto 0)
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28 | );
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29 | end Main;
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30 |
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31 | architecture Behavioral of Main is
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32 |
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33 | signal ADDR_rd : STD_LOGIC_VECTOR(23 downto 0);
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34 | signal ADDR_wr : STD_LOGIC_VECTOR(23 downto 0);
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35 | signal ueberlauf: STD_LOGIC;
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36 | signal WR_err : STD_LOGIC;
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37 | signal RD_err : STD_LOGIC;
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38 | type statetype is (get_data, write_data_ddr, write_data_ddr_wait, read_data, read_data_wait, transmit_data, idle);
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39 | signal state : statetype;
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40 |
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41 | begin
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42 | P1: Process(SYS_clk)
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43 | begin
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44 |
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45 |
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46 | if rising_edge(SYS_clk) then
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47 |
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48 | deb_ADDR_rd <= ADDR_rd; --: STD_LOGIC_VECTOR(23 downto 0);
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49 | deb_ADDR_wr <= ADDR_wr; --: STD_LOGIC_VECTOR(23 downto 0);
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50 | deb_ueberlauf <= ueberlauf; --: STD_LOGIC;
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51 | deb_WR_err <= WR_err; --: STD_LOGIC;
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52 | deb_RD_err <= RD_err; --: STD_LOGIC;
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53 |
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54 | if Reset = '1' then -- Reset Aktiv
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55 | UART_SEND_data_en <= '0';
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56 | BUFF_RD_sampled_data <= '0';
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57 | DDR_R_w <= '0';
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58 | DDR_R_w_en <= '0';
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59 | WR_err <= '0';
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60 | RD_err <= '0';
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61 | DDR_Address <= x"000000";
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62 | DDR_DATA_in <= x"0000000000000000";
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63 | UART_SEND_data <= x"0000000000000000";
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64 | ADDR_rd <= x"000000";
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65 | ADDR_wr <= x"000001";
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66 | ueberlauf <= '0';
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67 | DDR_empty <= '1';
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68 | state <= idle;
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69 | else -- Reset inaktiv
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70 | if state = idle then -- Wenn IDLE
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71 | deb_state <="000";
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72 | UART_SEND_data_en <= '0';
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73 | if BUFF_FIFO_empty = '0' then -- Wenn fifo != empty --> Lesen
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74 | BUFF_RD_sampled_data <= '1';
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75 | state <= get_data;
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76 | end if;
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77 | elsif state = get_data then -- Wenn daten von FIFO gelesen
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78 | deb_state <="001";
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79 | BUFF_RD_sampled_data <= '0';
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80 | DDR_DATA_in <= BUFF_SAMPLED_data_out;-- Daten puffern
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81 | state <= write_data_ddr;
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82 | elsif state = write_data_ddr then -- Daten in DDR schreiben
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83 | deb_state <="010";
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84 | if DDR_DDR2_rdy = '1' then -- Wenn DDR bereit --> Schreiben
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85 | DDR_Address <= ADDR_wr;
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86 | if ADDR_wr > ADDR_rd and ueberlauf = '0' then
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87 | DDR_R_w <= '0';
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88 | DDR_R_w_en <= '1';
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89 | if ADDR_wr < x"ffffff" then
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90 | --Wenn Maximal Addresse erreicht --> an addresse 0 beginnen, falls bereits ausgelesen
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91 | ADDR_wr <= ADDR_wr + 1;
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92 | state <= write_data_ddr_wait;
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93 | else
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94 | state <= write_data_ddr_wait;
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95 | ADDR_wr <= x"000000";
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96 | ueberlauf <= '1'; -- Setzen überlauf hat stattgefunden
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97 | end if;
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98 | elsif ADDR_wr < ADDR_rd and ueberlauf = '1' then
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99 | DDR_R_w <= '0';
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100 | DDR_R_w_en <= '1';
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101 | state <= write_data_ddr_wait;
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102 | ADDR_wr <= ADDR_wr + 1;
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103 | else
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104 | DDR_R_w <= '0';
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105 | DDR_R_w_en <= '0';
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106 | WR_err <= '1';
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107 | end if;
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108 | end if;
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109 | elsif state = write_data_ddr_wait then
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110 | deb_state <="011";
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111 | DDR_R_w_en <= '0';
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112 | state <= read_data;
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113 | elsif state = read_data then --Daten geschrieben
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114 | deb_state <="100";
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115 | if UART_SEND_ready = '1' then -- Wenn FIFO bereit Daten zu senden
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116 | if DDR_DDR2_rdy = '1' then -- Daten Lesen
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117 | DDR_Address <= ADDR_rd;
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118 | if ADDR_wr >= ADDR_rd and ueberlauf = '0' then
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119 | DDR_R_w <= '1';
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120 | DDR_R_w_en <= '1';
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121 | ADDR_rd <= ADDR_rd + 1;
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122 | state <= read_data_wait;
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123 | DDR_empty <= '0';
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124 | elsif ADDR_wr < ADDR_rd and ueberlauf = '1' then
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125 | DDR_R_w <= '1';
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126 | DDR_R_w_en <= '1';
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127 | state <= read_data_wait;
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128 | if ADDR_rd < x"ffffff" then
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129 | ADDR_rd <= ADDR_rd + 1;
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130 | else
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131 | ueberlauf <= '0';
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132 | ADDR_rd <= x"000000";
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133 | end if;
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134 | DDR_empty <= '0';
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135 | else
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136 | DDR_R_w <= '0';
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137 | DDR_R_w_en <= '0';
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138 | DDR_empty <= '1';
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139 | state <= idle;
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140 | end if;
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141 | end if;
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142 | else
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143 | DDR_R_w <= '0';
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144 | DDR_R_w_en <= '0';
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145 | state <= idle;
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146 | end if;
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147 | elsif state = read_data_wait then
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148 | deb_state <="101";
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149 | DDR_R_w_en <= '0';
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150 | DDR_R_w <= '0';
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151 | state <= transmit_data;
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152 | elsif state = transmit_data then
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153 | deb_state <="110";
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154 | DDR_R_w <= '0';
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155 | DDR_R_w_en <= '0';
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156 | if DDR_DDR2_rdy = '1' then
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157 | UART_SEND_data <= DDR_DATA_out;
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158 | UART_SEND_data_en <= '1';
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159 | state <= idle;
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160 | end if;
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161 | end if;
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162 | end if;
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163 | end if;
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164 | end Process;
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165 | end Behavioral;
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