library IEEE;
use IEEE.std_logic_1164.all;

entity COUNTER is
      Port (     CLK : In    STD_LOGIC;
              ENABLE : In    STD_LOGIC;
                MODE : In    STD_LOGIC;
              REG_IN : In    std_logic_vector (3 downto 0);
                 RES : In    STD_LOGIC;
              PC_OUT : Out   std_logic_vector (3 downto 0) );
end COUNTER;

architecture BEHAVIORAL of COUNTER is
  signal pc_state: std_logic_vector (3 downto 0);
begin

  PC_OUT <= pc_state;
  
  process (clk, RES)
  begin
    if (RES = '1') then pc_state <= "0000"; -- Reset asynchron
   end if;
    
   if (ENABLE = '1') then
     if (clk='1' and clk'event) then
        if (MODE = '1') then 
        pc_state <= REG_IN; 
      end if;
      
        if (MODE = '0') then 
        if (pc_state="1111") then
          pc_state <= "0000";  -- Overflow
       else
           pc_state <= pc_state + 1;
       end if;
      end if;
     end if;
    end if;
  end process;

end BEHAVIORAL;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

process(reset,clk)
begin
 if resest = '1' then
   -- mach was;
 elsif clk='1' AND clk'event then
   -- und noch was;
 end if; 
end process;