Equations

********** Mapped Logic **********
FTCPE_cnt0: FTCPE port map (cnt(0),'1',clk,'0','0');
FTCPE_cnt1: FTCPE port map (cnt(1),cnt(0),clk,'0','0');
FTCPE_cnt2: FTCPE port map (cnt(2),cnt_T(2),clk,'0','0');
     cnt_T(2) <= (cnt(0) AND cnt(1));
FTCPE_cnt3: FTCPE port map (cnt(3),cnt_T(3),clk,'0','0');
     cnt_T(3) <= (cnt(0) AND cnt(1) AND cnt(2));
FTCPE_cnt4: FTCPE port map (cnt(4),cnt_T(4),clk,'0','0');
     cnt_T(4) <= (cnt(0) AND cnt(1) AND cnt(2) AND cnt(3));
FTCPE_cnt5: FTCPE port map (cnt(5),cnt_T(5),clk,'0','0');
     cnt_T(5) <= (cnt(0) AND cnt(1) AND cnt(2) AND cnt(3) AND cnt(4));
FTCPE_cnt6: FTCPE port map (cnt(6),cnt_T(6),clk,'0','0');
     cnt_T(6) <= (cnt(0) AND cnt(1) AND cnt(2) AND cnt(3) AND cnt(4) AND
      cnt(5));
FTCPE_cnt7: FTCPE port map (cnt(7),cnt_T(7),clk,'0','0');
     cnt_T(7) <= (cnt(0) AND cnt(1) AND cnt(2) AND cnt(3) AND cnt(4) AND
      cnt(5) AND cnt(6));
FTCPE_cnt8: FTCPE port map (cnt(8),cnt_T(8),clk,'0','0');
     cnt_T(8) <= (cnt(0) AND cnt(1) AND cnt(2) AND cnt(3) AND cnt(4) AND
      cnt(5) AND cnt(6) AND cnt(7));
FTCPE_cnt9: FTCPE port map (cnt(9),cnt_T(9),clk,'0','0');
     cnt_T(9) <= (cnt(0) AND cnt(1) AND cnt(2) AND cnt(3) AND cnt(4) AND
      cnt(5) AND cnt(6) AND cnt(7) AND cnt(8));
FTCPE_cnt10: FTCPE port map (cnt(10),cnt_T(10),clk,'0','0');
     cnt_T(10) <= (cnt(0) AND cnt(1) AND cnt(2) AND cnt(3) AND cnt(4) AND
      cnt(5) AND cnt(6) AND cnt(7) AND cnt(8) AND cnt(9));
FTCPE_cnt11: FTCPE port map (cnt(11),cnt_T(11),clk,'0','0');
     cnt_T(11) <= (cnt(0) AND cnt(10) AND cnt(1) AND cnt(2) AND cnt(3) AND
      cnt(4) AND cnt(5) AND cnt(6) AND cnt(7) AND cnt(8) AND cnt(9));
FTCPE_cnt12: FTCPE port map (cnt(12),cnt_T(12),clk,'0','0');
     cnt_T(12) <= (cnt(0) AND cnt(10) AND cnt(11) AND cnt(1) AND cnt(2) AND
      cnt(3) AND cnt(4) AND cnt(5) AND cnt(6) AND cnt(7) AND cnt(8) AND
      cnt(9));
FTCPE_cnt13: FTCPE port map (cnt(13),cnt_T(13),clk,'0','0');
     cnt_T(13) <= (cnt(0) AND cnt(10) AND cnt(11) AND cnt(12) AND cnt(1) AND
      cnt(2) AND cnt(3) AND cnt(4) AND cnt(5) AND cnt(6) AND cnt(7) AND
      cnt(8) AND cnt(9));
FTCPE_cnt14: FTCPE port map (cnt(14),cnt_T(14),clk,'0','0');
     cnt_T(14) <= (cnt(0) AND cnt(10) AND cnt(11) AND cnt(12) AND cnt(13) AND
      cnt(1) AND cnt(2) AND cnt(3) AND cnt(4) AND cnt(5) AND cnt(6) AND
      cnt(7) AND cnt(8) AND cnt(9));
FTCPE_cnt15: FTCPE port map (cnt(15),cnt_T(15),clk,'0','0');
     cnt_T(15) <= (cnt(0) AND cnt(10) AND cnt(11) AND cnt(12) AND cnt(13) AND
      cnt(14) AND cnt(1) AND cnt(2) AND cnt(3) AND cnt(4) AND cnt(5) AND
      cnt(6) AND cnt(7) AND cnt(8) AND cnt(9));
FTCPE_cnt16: FTCPE port map (cnt(16),cnt_T(16),clk,'0','0');
     cnt_T(16) <= (cnt(0) AND cnt(10) AND cnt(11) AND cnt(12) AND cnt(13) AND
      cnt(14) AND cnt(15) AND cnt(1) AND cnt(2) AND cnt(3) AND cnt(4) AND
      cnt(5) AND cnt(6) AND cnt(7) AND cnt(8) AND cnt(9));
FTCPE_cnt17: FTCPE port map (cnt(17),cnt_T(17),clk,'0','0');
     cnt_T(17) <= (cnt(0) AND cnt(10) AND cnt(11) AND cnt(12) AND cnt(13) AND
      cnt(14) AND cnt(15) AND cnt(16) AND cnt(1) AND cnt(2) AND cnt(3) AND
      cnt(4) AND cnt(5) AND cnt(6) AND cnt(7) AND cnt(8) AND cnt(9));
FTCPE_cnt18: FTCPE port map (cnt(18),cnt_T(18),clk,'0','0');
     cnt_T(18) <= (cnt(0) AND cnt(10) AND cnt(11) AND cnt(12) AND cnt(13) AND
      cnt(14) AND cnt(15) AND cnt(16) AND cnt(17) AND cnt(1) AND cnt(2) AND
      cnt(3) AND cnt(4) AND cnt(5) AND cnt(6) AND cnt(7) AND cnt(8) AND
      cnt(9));
FTCPE_cnt19: FTCPE port map (cnt(19),cnt_T(19),clk,'0','0');
     cnt_T(19) <= (cnt(0) AND cnt(10) AND cnt(11) AND cnt(12) AND cnt(13) AND
      cnt(14) AND cnt(15) AND cnt(16) AND cnt(17) AND cnt(18) AND cnt(1) AND
      cnt(2) AND cnt(3) AND cnt(4) AND cnt(5) AND cnt(6) AND cnt(7) AND
      cnt(8) AND cnt(9));
FTCPE_cnt20: FTCPE port map (cnt(20),cnt_T(20),clk,'0','0');
     cnt_T(20) <= (cnt(0) AND cnt(10) AND cnt(11) AND cnt(12) AND cnt(13) AND
      cnt(14) AND cnt(15) AND cnt(16) AND cnt(17) AND cnt(18) AND
      cnt(19) AND cnt(1) AND cnt(2) AND cnt(3) AND cnt(4) AND cnt(5) AND
      cnt(6) AND cnt(7) AND cnt(8) AND cnt(9));
FTCPE_cnt21: FTCPE port map (cnt(21),cnt_T(21),clk,'0','0');
     cnt_T(21) <= (cnt(0) AND cnt(10) AND cnt(11) AND cnt(12) AND cnt(13) AND
      cnt(14) AND cnt(15) AND cnt(16) AND cnt(17) AND cnt(18) AND
      cnt(19) AND cnt(1) AND cnt(20) AND cnt(2) AND cnt(3) AND cnt(4) AND
      cnt(5) AND cnt(6) AND cnt(7) AND cnt(8) AND cnt(9));
FTCPE_cnt22: FTCPE port map (cnt(22),cnt_T(22),clk,'0','0');
     cnt_T(22) <= (cnt(0) AND cnt(10) AND cnt(11) AND cnt(12) AND cnt(13) AND
      cnt(14) AND cnt(15) AND cnt(16) AND cnt(17) AND cnt(18) AND
      cnt(19) AND cnt(1) AND cnt(20) AND cnt(21) AND cnt(2) AND cnt(3) AND
      cnt(4) AND cnt(5) AND cnt(6) AND cnt(7) AND cnt(8) AND cnt(9));
FTCPE_cnt24: FTCPE port map (cnt(24),cnt_T(24),clk,'0','0');
     cnt_T(24) <= (led1 AND cnt(0) AND cnt(10) AND cnt(11) AND cnt(12) AND
      cnt(13) AND cnt(14) AND cnt(15) AND cnt(16) AND cnt(17) AND
      cnt(18) AND cnt(19) AND cnt(1) AND cnt(20) AND cnt(21) AND cnt(22) AND
      cnt(2) AND cnt(3) AND cnt(4) AND cnt(5) AND cnt(6) AND cnt(7) AND
      cnt(8) AND cnt(9));
FTCPE_cnt26: FTCPE port map (cnt(26),cnt_T(26),clk,'0','0');
     cnt_T(26) <= (led1 AND led2 AND cnt(0) AND cnt(10) AND cnt(11) AND
      cnt(12) AND cnt(13) AND cnt(14) AND cnt(15) AND cnt(16) AND
      cnt(17) AND cnt(18) AND cnt(19) AND cnt(1) AND cnt(20) AND cnt(21) AND
      cnt(22) AND cnt(24) AND cnt(2) AND cnt(3) AND cnt(4) AND cnt(5) AND
      cnt(6) AND cnt(7) AND cnt(8) AND cnt(9));
FTCPE_led1: FTCPE port map (led1,led1_T,clk,'0','0');
     led1_T <= (cnt(0) AND cnt(10) AND cnt(11) AND cnt(12) AND cnt(13) AND
      cnt(14) AND cnt(15) AND cnt(16) AND cnt(17) AND cnt(18) AND
      cnt(19) AND cnt(1) AND cnt(20) AND cnt(21) AND cnt(22) AND cnt(2) AND
      cnt(3) AND cnt(4) AND cnt(5) AND cnt(6) AND cnt(7) AND cnt(8) AND
      cnt(9));
FTCPE_led2: FTCPE port map (led2,led2_T,clk,'0','0');
     led2_T <= (led1 AND cnt(0) AND cnt(10) AND cnt(11) AND cnt(12) AND
      cnt(13) AND cnt(14) AND cnt(15) AND cnt(16) AND cnt(17) AND
      cnt(18) AND cnt(19) AND cnt(1) AND cnt(20) AND cnt(21) AND cnt(22) AND
      cnt(24) AND cnt(2) AND cnt(3) AND cnt(4) AND cnt(5) AND cnt(6) AND
      cnt(7) AND cnt(8) AND cnt(9));
FTCPE_led3: FTCPE port map (led3,led3_T,clk,'0','0');
     led3_T <= (led1 AND led2 AND cnt(0) AND cnt(10) AND cnt(11) AND
      cnt(12) AND cnt(13) AND cnt(14) AND cnt(15) AND cnt(16) AND
      cnt(17) AND cnt(18) AND cnt(19) AND cnt(1) AND cnt(20) AND cnt(21) AND
      cnt(22) AND cnt(24) AND cnt(26) AND cnt(2) AND cnt(3) AND cnt(4) AND
      cnt(5) AND cnt(6) AND cnt(7) AND cnt(8) AND cnt(9));
Register Legend:
      FDCPE (Q,D,C,CLR,PRE,CE);
      FTCPE (Q,D,C,CLR,PRE,CE);
      LDCP (Q,D,G,CLR,PRE);