================================================================================ Timing constraint: TS_CLK_in = PERIOD TIMEGRP "CLK_in" 48 MHz HIGH 50% INPUT_JITTER 0.0021 ns; 7377055 paths analyzed, 15710 endpoints analyzed, 0 failing endpoints 0 timing errors detected. (0 setup errors, 0 hold errors, 0 component switching limit errors) Minimum period is 19.557ns. -------------------------------------------------------------------------------- Paths for end point CCP_Inst/C_Inst/StateMachine.Progress_FSM_FFd5 (SLICE_X34Y58.C3), 13925 paths -------------------------------------------------------------------------------- Slack (setup path): 1.276ns (requirement - (data path - clock path skew + uncertainty)) Source: CCP_Inst/C_Inst/MTBus_Address_11 (FF) Destination: CCP_Inst/C_Inst/StateMachine.Progress_FSM_FFd5 (FF) Requirement: 20.833ns Data Path Delay: 19.460ns (Levels of Logic = 11) Clock Path Skew: -0.062ns (0.704 - 0.766) Source Clock: CLK_in_BUFGP rising at 0.000ns Destination Clock: CLK_in_BUFGP rising at 20.833ns Clock Uncertainty: 0.035ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.070ns Total Input Jitter (TIJ): 0.002ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Maximum Data Path at Slow Process Corner: CCP_Inst/C_Inst/MTBus_Address_11 to CCP_Inst/C_Inst/StateMachine.Progress_FSM_FFd5 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X23Y68.CQ Tcko 0.548 CCP_Inst/C_Inst/MTBus_Address<11> CCP_Inst/C_Inst/MTBus_Address_11 SLICE_X32Y62.C3 net (fanout=18) 3.385 CCP_Inst/C_Inst/MTBus_Address<11> SLICE_X32Y62.COUT Topcyc 0.471 CCP_Inst/C_Inst/Madd_MTBus_Address[31]_GND_31_o_add_121_OUT_cy<12> CCP_Inst/C_Inst/MTBus_Address<11>_rt.1 CCP_Inst/C_Inst/Madd_MTBus_Address[31]_GND_31_o_add_121_OUT_cy<12> SLICE_X32Y63.CIN net (fanout=1) 0.003 CCP_Inst/C_Inst/Madd_MTBus_Address[31]_GND_31_o_add_121_OUT_cy<12> SLICE_X32Y63.COUT Tbyp 0.123 CCP_Inst/C_Inst/Madd_MTBus_Address[31]_GND_31_o_add_121_OUT_cy<16> CCP_Inst/C_Inst/Madd_MTBus_Address[31]_GND_31_o_add_121_OUT_cy<16> SLICE_X32Y64.CIN net (fanout=1) 0.206 CCP_Inst/C_Inst/Madd_MTBus_Address[31]_GND_31_o_add_121_OUT_cy<16> SLICE_X32Y64.COUT Tbyp 0.123 CCP_Inst/C_Inst/Madd_MTBus_Address[31]_GND_31_o_add_121_OUT_cy<20> CCP_Inst/C_Inst/Madd_MTBus_Address[31]_GND_31_o_add_121_OUT_cy<20> SLICE_X32Y65.CIN net (fanout=1) 0.003 CCP_Inst/C_Inst/Madd_MTBus_Address[31]_GND_31_o_add_121_OUT_cy<20> SLICE_X32Y65.COUT Tbyp 0.123 CCP_Inst/C_Inst/Madd_MTBus_Address[31]_GND_31_o_add_121_OUT_cy<24> CCP_Inst/C_Inst/Madd_MTBus_Address[31]_GND_31_o_add_121_OUT_cy<24> SLICE_X32Y66.CIN net (fanout=1) 0.003 CCP_Inst/C_Inst/Madd_MTBus_Address[31]_GND_31_o_add_121_OUT_cy<24> SLICE_X32Y66.AMUX Tcina 0.285 CCP_Inst/C_Inst/Madd_MTBus_Address[31]_GND_31_o_add_121_OUT_cy<28> CCP_Inst/C_Inst/Madd_MTBus_Address[31]_GND_31_o_add_121_OUT_cy<28> SLICE_X34Y61.B1 net (fanout=1) 1.710 CCP_Inst/C_Inst/MTBus_Address[31]_GND_31_o_add_121_OUT<25> SLICE_X34Y61.CMUX Topbc 0.907 CCP_Inst/C_Inst/GND_31_o_PWR_39_o_MUX_1158_o CCP_Inst/C_Inst/Mcompar_GND_31_o_MTBus_Address[31]_LessThan_123_o_lut<5> CCP_Inst/C_Inst/GND_31_o_PWR_39_o_MUX_1158_o1_cy SLICE_X27Y67.A4 net (fanout=14) 2.084 CCP_Inst/C_Inst/Mcompar_GND_31_o_MTBus_Address[31]_LessThan_123_o_cy<6> SLICE_X27Y67.A Tilo 0.341 CCP_Inst/C_Inst/N1194 CCP_Inst/C_Inst/GND_31_o_StateMachine.Step[2]_equal_142_o<2>1 SLICE_X47Y46.A6 net (fanout=44) 3.718 CCP_Inst/C_Inst/GND_31_o_StateMachine.Step[2]_equal_142_o SLICE_X47Y46.A Tilo 0.341 CCP_Inst/C_Inst/Mmux_StateMachine.Progress[2]_Task[4]_mux_482_OUT16 CCP_Inst/C_Inst/Mmux_StateMachine.Progress[2]_Task[4]_mux_482_OUT17 SLICE_X40Y46.A6 net (fanout=2) 0.986 CCP_Inst/C_Inst/Mmux_StateMachine.Progress[2]_Task[4]_mux_482_OUT16 SLICE_X40Y46.A Tilo 0.333 N883 CCP_Inst/C_Inst/Mmux_StateMachine.Progress[2]_Task[4]_mux_482_OUT110_SW2 SLICE_X40Y54.C1 net (fanout=1) 1.494 N883 SLICE_X40Y54.C Tilo 0.333 CCP_Inst/C_Inst/StateMachine.Step_FSM_FFd5_2 CCP_Inst/C_Inst/Mmux_StateMachine.Progress[2]_Task[4]_mux_482_OUT113 SLICE_X34Y58.C3 net (fanout=11) 1.417 CCP_Inst/C_Inst/StateMachine.Progress[2]_Task[4]_mux_482_OUT<0> SLICE_X34Y58.CLK Tas 0.523 CCP_Inst/C_Inst/StateMachine.Progress_FSM_FFd5 CCP_Inst/C_Inst/StateMachine.Progress_FSM_FFd5-In6 CCP_Inst/C_Inst/StateMachine.Progress_FSM_FFd5 ------------------------------------------------- --------------------------- Total 19.460ns (4.451ns logic, 15.009ns route) (22.9% logic, 77.1% route) -------------------------------------------------------------------------------- Slack (setup path): 1.392ns (requirement - (data path - clock path skew + uncertainty)) Source: CCP_Inst/C_Inst/MTBus_Address_11 (FF) Destination: CCP_Inst/C_Inst/StateMachine.Progress_FSM_FFd5 (FF) Requirement: 20.833ns Data Path Delay: 19.344ns (Levels of Logic = 11) Clock Path Skew: -0.062ns (0.704 - 0.766) Source Clock: CLK_in_BUFGP rising at 0.000ns Destination Clock: CLK_in_BUFGP rising at 20.833ns Clock Uncertainty: 0.035ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.070ns Total Input Jitter (TIJ): 0.002ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Maximum Data Path at Slow Process Corner: CCP_Inst/C_Inst/MTBus_Address_11 to CCP_Inst/C_Inst/StateMachine.Progress_FSM_FFd5 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X23Y68.CQ Tcko 0.548 CCP_Inst/C_Inst/MTBus_Address<11> CCP_Inst/C_Inst/MTBus_Address_11 SLICE_X32Y62.C3 net (fanout=18) 3.385 CCP_Inst/C_Inst/MTBus_Address<11> SLICE_X32Y62.COUT Topcyc 0.471 CCP_Inst/C_Inst/Madd_MTBus_Address[31]_GND_31_o_add_121_OUT_cy<12> CCP_Inst/C_Inst/MTBus_Address<11>_rt.1 CCP_Inst/C_Inst/Madd_MTBus_Address[31]_GND_31_o_add_121_OUT_cy<12> SLICE_X32Y63.CIN net (fanout=1) 0.003 CCP_Inst/C_Inst/Madd_MTBus_Address[31]_GND_31_o_add_121_OUT_cy<12> SLICE_X32Y63.COUT Tbyp 0.123 CCP_Inst/C_Inst/Madd_MTBus_Address[31]_GND_31_o_add_121_OUT_cy<16> CCP_Inst/C_Inst/Madd_MTBus_Address[31]_GND_31_o_add_121_OUT_cy<16> SLICE_X32Y64.CIN net (fanout=1) 0.206 CCP_Inst/C_Inst/Madd_MTBus_Address[31]_GND_31_o_add_121_OUT_cy<16> SLICE_X32Y64.COUT Tbyp 0.123 CCP_Inst/C_Inst/Madd_MTBus_Address[31]_GND_31_o_add_121_OUT_cy<20> CCP_Inst/C_Inst/Madd_MTBus_Address[31]_GND_31_o_add_121_OUT_cy<20> SLICE_X32Y65.CIN net (fanout=1) 0.003 CCP_Inst/C_Inst/Madd_MTBus_Address[31]_GND_31_o_add_121_OUT_cy<20> SLICE_X32Y65.COUT Tbyp 0.123 CCP_Inst/C_Inst/Madd_MTBus_Address[31]_GND_31_o_add_121_OUT_cy<24> CCP_Inst/C_Inst/Madd_MTBus_Address[31]_GND_31_o_add_121_OUT_cy<24> SLICE_X32Y66.CIN net (fanout=1) 0.003 CCP_Inst/C_Inst/Madd_MTBus_Address[31]_GND_31_o_add_121_OUT_cy<24> SLICE_X32Y66.AMUX Tcina 0.285 CCP_Inst/C_Inst/Madd_MTBus_Address[31]_GND_31_o_add_121_OUT_cy<28> CCP_Inst/C_Inst/Madd_MTBus_Address[31]_GND_31_o_add_121_OUT_cy<28> SLICE_X34Y61.B1 net (fanout=1) 1.710 CCP_Inst/C_Inst/MTBus_Address[31]_GND_31_o_add_121_OUT<25> SLICE_X34Y61.CMUX Topbc 0.907 CCP_Inst/C_Inst/GND_31_o_PWR_39_o_MUX_1158_o CCP_Inst/C_Inst/Mcompar_GND_31_o_MTBus_Address[31]_LessThan_123_o_lut<5> CCP_Inst/C_Inst/GND_31_o_PWR_39_o_MUX_1158_o1_cy SLICE_X27Y67.A4 net (fanout=14) 2.084 CCP_Inst/C_Inst/Mcompar_GND_31_o_MTBus_Address[31]_LessThan_123_o_cy<6> SLICE_X27Y67.A Tilo 0.341 CCP_Inst/C_Inst/N1194 CCP_Inst/C_Inst/GND_31_o_StateMachine.Step[2]_equal_142_o<2>1 SLICE_X47Y46.A6 net (fanout=44) 3.718 CCP_Inst/C_Inst/GND_31_o_StateMachine.Step[2]_equal_142_o SLICE_X47Y46.A Tilo 0.341 CCP_Inst/C_Inst/Mmux_StateMachine.Progress[2]_Task[4]_mux_482_OUT16 CCP_Inst/C_Inst/Mmux_StateMachine.Progress[2]_Task[4]_mux_482_OUT17 SLICE_X45Y46.C4 net (fanout=2) 0.580 CCP_Inst/C_Inst/Mmux_StateMachine.Progress[2]_Task[4]_mux_482_OUT16 SLICE_X45Y46.C Tilo 0.341 CCP_Inst/C_Inst/Mmux_StateMachine.Progress[2]_Task[4]_mux_482_OUT18 CCP_Inst/C_Inst/Mmux_StateMachine.Progress[2]_Task[4]_mux_482_OUT110_SW0 SLICE_X40Y54.C3 net (fanout=1) 1.776 N881 SLICE_X40Y54.C Tilo 0.333 CCP_Inst/C_Inst/StateMachine.Step_FSM_FFd5_2 CCP_Inst/C_Inst/Mmux_StateMachine.Progress[2]_Task[4]_mux_482_OUT113 SLICE_X34Y58.C3 net (fanout=11) 1.417 CCP_Inst/C_Inst/StateMachine.Progress[2]_Task[4]_mux_482_OUT<0> SLICE_X34Y58.CLK Tas 0.523 CCP_Inst/C_Inst/StateMachine.Progress_FSM_FFd5 CCP_Inst/C_Inst/StateMachine.Progress_FSM_FFd5-In6 CCP_Inst/C_Inst/StateMachine.Progress_FSM_FFd5 ------------------------------------------------- --------------------------- Total 19.344ns (4.459ns logic, 14.885ns route) (23.1% logic, 76.9% route) -------------------------------------------------------------------------------- Slack (setup path): 1.401ns (requirement - (data path - clock path skew + uncertainty)) Source: CCP_Inst/C_Inst/MTBus_Address_11 (FF) Destination: CCP_Inst/C_Inst/StateMachine.Progress_FSM_FFd5 (FF) Requirement: 20.833ns Data Path Delay: 19.335ns (Levels of Logic = 12) Clock Path Skew: -0.062ns (0.704 - 0.766) Source Clock: CLK_in_BUFGP rising at 0.000ns Destination Clock: CLK_in_BUFGP rising at 20.833ns Clock Uncertainty: 0.035ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.070ns Total Input Jitter (TIJ): 0.002ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Maximum Data Path at Slow Process Corner: CCP_Inst/C_Inst/MTBus_Address_11 to CCP_Inst/C_Inst/StateMachine.Progress_FSM_FFd5 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X23Y68.CQ Tcko 0.548 CCP_Inst/C_Inst/MTBus_Address<11> CCP_Inst/C_Inst/MTBus_Address_11 SLICE_X32Y62.C3 net (fanout=18) 3.385 CCP_Inst/C_Inst/MTBus_Address<11> SLICE_X32Y62.COUT Topcyc 0.471 CCP_Inst/C_Inst/Madd_MTBus_Address[31]_GND_31_o_add_121_OUT_cy<12> CCP_Inst/C_Inst/MTBus_Address<11>_rt.1 CCP_Inst/C_Inst/Madd_MTBus_Address[31]_GND_31_o_add_121_OUT_cy<12> SLICE_X32Y63.CIN net (fanout=1) 0.003 CCP_Inst/C_Inst/Madd_MTBus_Address[31]_GND_31_o_add_121_OUT_cy<12> SLICE_X32Y63.COUT Tbyp 0.123 CCP_Inst/C_Inst/Madd_MTBus_Address[31]_GND_31_o_add_121_OUT_cy<16> CCP_Inst/C_Inst/Madd_MTBus_Address[31]_GND_31_o_add_121_OUT_cy<16> SLICE_X32Y64.CIN net (fanout=1) 0.206 CCP_Inst/C_Inst/Madd_MTBus_Address[31]_GND_31_o_add_121_OUT_cy<16> SLICE_X32Y64.COUT Tbyp 0.123 CCP_Inst/C_Inst/Madd_MTBus_Address[31]_GND_31_o_add_121_OUT_cy<20> CCP_Inst/C_Inst/Madd_MTBus_Address[31]_GND_31_o_add_121_OUT_cy<20> SLICE_X32Y65.CIN net (fanout=1) 0.003 CCP_Inst/C_Inst/Madd_MTBus_Address[31]_GND_31_o_add_121_OUT_cy<20> SLICE_X32Y65.COUT Tbyp 0.123 CCP_Inst/C_Inst/Madd_MTBus_Address[31]_GND_31_o_add_121_OUT_cy<24> CCP_Inst/C_Inst/Madd_MTBus_Address[31]_GND_31_o_add_121_OUT_cy<24> SLICE_X32Y66.CIN net (fanout=1) 0.003 CCP_Inst/C_Inst/Madd_MTBus_Address[31]_GND_31_o_add_121_OUT_cy<24> SLICE_X32Y66.COUT Tbyp 0.123 CCP_Inst/C_Inst/Madd_MTBus_Address[31]_GND_31_o_add_121_OUT_cy<28> CCP_Inst/C_Inst/Madd_MTBus_Address[31]_GND_31_o_add_121_OUT_cy<28> SLICE_X32Y67.CIN net (fanout=1) 0.003 CCP_Inst/C_Inst/Madd_MTBus_Address[31]_GND_31_o_add_121_OUT_cy<28> SLICE_X32Y67.CMUX Tcinc 0.434 CCP_Inst/C_Inst/MTBus_Address[31]_GND_31_o_add_121_OUT<31> CCP_Inst/C_Inst/Madd_MTBus_Address[31]_GND_31_o_add_121_OUT_xor<31> SLICE_X34Y61.C1 net (fanout=1) 1.609 CCP_Inst/C_Inst/MTBus_Address[31]_GND_31_o_add_121_OUT<31> SLICE_X34Y61.CMUX Topcc 0.608 CCP_Inst/C_Inst/GND_31_o_PWR_39_o_MUX_1158_o CCP_Inst/C_Inst/Mcompar_GND_31_o_MTBus_Address[31]_LessThan_123_o_lut<6> CCP_Inst/C_Inst/GND_31_o_PWR_39_o_MUX_1158_o1_cy SLICE_X27Y67.A4 net (fanout=14) 2.084 CCP_Inst/C_Inst/Mcompar_GND_31_o_MTBus_Address[31]_LessThan_123_o_cy<6> SLICE_X27Y67.A Tilo 0.341 CCP_Inst/C_Inst/N1194 CCP_Inst/C_Inst/GND_31_o_StateMachine.Step[2]_equal_142_o<2>1 SLICE_X47Y46.A6 net (fanout=44) 3.718 CCP_Inst/C_Inst/GND_31_o_StateMachine.Step[2]_equal_142_o SLICE_X47Y46.A Tilo 0.341 CCP_Inst/C_Inst/Mmux_StateMachine.Progress[2]_Task[4]_mux_482_OUT16 CCP_Inst/C_Inst/Mmux_StateMachine.Progress[2]_Task[4]_mux_482_OUT17 SLICE_X40Y46.A6 net (fanout=2) 0.986 CCP_Inst/C_Inst/Mmux_StateMachine.Progress[2]_Task[4]_mux_482_OUT16 SLICE_X40Y46.A Tilo 0.333 N883 CCP_Inst/C_Inst/Mmux_StateMachine.Progress[2]_Task[4]_mux_482_OUT110_SW2 SLICE_X40Y54.C1 net (fanout=1) 1.494 N883 SLICE_X40Y54.C Tilo 0.333 CCP_Inst/C_Inst/StateMachine.Step_FSM_FFd5_2 CCP_Inst/C_Inst/Mmux_StateMachine.Progress[2]_Task[4]_mux_482_OUT113 SLICE_X34Y58.C3 net (fanout=11) 1.417 CCP_Inst/C_Inst/StateMachine.Progress[2]_Task[4]_mux_482_OUT<0> SLICE_X34Y58.CLK Tas 0.523 CCP_Inst/C_Inst/StateMachine.Progress_FSM_FFd5 CCP_Inst/C_Inst/StateMachine.Progress_FSM_FFd5-In6 CCP_Inst/C_Inst/StateMachine.Progress_FSM_FFd5 ------------------------------------------------- --------------------------- Total 19.335ns (4.424ns logic, 14.911ns route) (22.9% logic, 77.1% route) -------------------------------------------------------------------------------- Paths for end point CCP_Inst/C_Inst/fsmfake3_0 (SLICE_X45Y61.A4), 13925 paths -------------------------------------------------------------------------------- Slack (setup path): 1.310ns (requirement - (data path - clock path skew + uncertainty)) Source: CCP_Inst/C_Inst/MTBus_Address_11 (FF) Destination: CCP_Inst/C_Inst/fsmfake3_0 (FF) Requirement: 20.833ns Data Path Delay: 19.430ns (Levels of Logic = 11) Clock Path Skew: -0.058ns (0.708 - 0.766) Source Clock: CLK_in_BUFGP rising at 0.000ns Destination Clock: CLK_in_BUFGP rising at 20.833ns Clock Uncertainty: 0.035ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.070ns Total Input Jitter (TIJ): 0.002ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Maximum Data Path at Slow Process Corner: CCP_Inst/C_Inst/MTBus_Address_11 to CCP_Inst/C_Inst/fsmfake3_0 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X23Y68.CQ Tcko 0.548 CCP_Inst/C_Inst/MTBus_Address<11> CCP_Inst/C_Inst/MTBus_Address_11 SLICE_X32Y62.C3 net (fanout=18) 3.385 CCP_Inst/C_Inst/MTBus_Address<11> SLICE_X32Y62.COUT Topcyc 0.471 CCP_Inst/C_Inst/Madd_MTBus_Address[31]_GND_31_o_add_121_OUT_cy<12> CCP_Inst/C_Inst/MTBus_Address<11>_rt.1 CCP_Inst/C_Inst/Madd_MTBus_Address[31]_GND_31_o_add_121_OUT_cy<12> SLICE_X32Y63.CIN net (fanout=1) 0.003 CCP_Inst/C_Inst/Madd_MTBus_Address[31]_GND_31_o_add_121_OUT_cy<12> SLICE_X32Y63.COUT Tbyp 0.123 CCP_Inst/C_Inst/Madd_MTBus_Address[31]_GND_31_o_add_121_OUT_cy<16> CCP_Inst/C_Inst/Madd_MTBus_Address[31]_GND_31_o_add_121_OUT_cy<16> SLICE_X32Y64.CIN net (fanout=1) 0.206 CCP_Inst/C_Inst/Madd_MTBus_Address[31]_GND_31_o_add_121_OUT_cy<16> SLICE_X32Y64.COUT Tbyp 0.123 CCP_Inst/C_Inst/Madd_MTBus_Address[31]_GND_31_o_add_121_OUT_cy<20> CCP_Inst/C_Inst/Madd_MTBus_Address[31]_GND_31_o_add_121_OUT_cy<20> SLICE_X32Y65.CIN net (fanout=1) 0.003 CCP_Inst/C_Inst/Madd_MTBus_Address[31]_GND_31_o_add_121_OUT_cy<20> SLICE_X32Y65.COUT Tbyp 0.123 CCP_Inst/C_Inst/Madd_MTBus_Address[31]_GND_31_o_add_121_OUT_cy<24> CCP_Inst/C_Inst/Madd_MTBus_Address[31]_GND_31_o_add_121_OUT_cy<24> SLICE_X32Y66.CIN net (fanout=1) 0.003 CCP_Inst/C_Inst/Madd_MTBus_Address[31]_GND_31_o_add_121_OUT_cy<24> SLICE_X32Y66.AMUX Tcina 0.285 CCP_Inst/C_Inst/Madd_MTBus_Address[31]_GND_31_o_add_121_OUT_cy<28> CCP_Inst/C_Inst/Madd_MTBus_Address[31]_GND_31_o_add_121_OUT_cy<28> SLICE_X34Y61.B1 net (fanout=1) 1.710 CCP_Inst/C_Inst/MTBus_Address[31]_GND_31_o_add_121_OUT<25> SLICE_X34Y61.CMUX Topbc 0.907 CCP_Inst/C_Inst/GND_31_o_PWR_39_o_MUX_1158_o CCP_Inst/C_Inst/Mcompar_GND_31_o_MTBus_Address[31]_LessThan_123_o_lut<5> CCP_Inst/C_Inst/GND_31_o_PWR_39_o_MUX_1158_o1_cy SLICE_X27Y67.A4 net (fanout=14) 2.084 CCP_Inst/C_Inst/Mcompar_GND_31_o_MTBus_Address[31]_LessThan_123_o_cy<6> SLICE_X27Y67.A Tilo 0.341 CCP_Inst/C_Inst/N1194 CCP_Inst/C_Inst/GND_31_o_StateMachine.Step[2]_equal_142_o<2>1 SLICE_X47Y46.A6 net (fanout=44) 3.718 CCP_Inst/C_Inst/GND_31_o_StateMachine.Step[2]_equal_142_o SLICE_X47Y46.A Tilo 0.341 CCP_Inst/C_Inst/Mmux_StateMachine.Progress[2]_Task[4]_mux_482_OUT16 CCP_Inst/C_Inst/Mmux_StateMachine.Progress[2]_Task[4]_mux_482_OUT17 SLICE_X40Y46.A6 net (fanout=2) 0.986 CCP_Inst/C_Inst/Mmux_StateMachine.Progress[2]_Task[4]_mux_482_OUT16 SLICE_X40Y46.A Tilo 0.333 N883 CCP_Inst/C_Inst/Mmux_StateMachine.Progress[2]_Task[4]_mux_482_OUT110_SW2 SLICE_X40Y54.C1 net (fanout=1) 1.494 N883 SLICE_X40Y54.C Tilo 0.333 CCP_Inst/C_Inst/StateMachine.Step_FSM_FFd5_2 CCP_Inst/C_Inst/Mmux_StateMachine.Progress[2]_Task[4]_mux_482_OUT113 SLICE_X45Y61.A4 net (fanout=11) 1.405 CCP_Inst/C_Inst/StateMachine.Progress[2]_Task[4]_mux_482_OUT<0> SLICE_X45Y61.CLK Tas 0.505 CCP_Inst/C_Inst/fsmfake3<2> CCP_Inst/C_Inst/Mmux_StateMachine.Step[2]_StateMachine.Step[2]_mux_513_OUT618 CCP_Inst/C_Inst/fsmfake3_0 ------------------------------------------------- --------------------------- Total 19.430ns (4.433ns logic, 14.997ns route) (22.8% logic, 77.2% route) -------------------------------------------------------------------------------- Slack (setup path): 1.426ns (requirement - (data path - clock path skew + uncertainty)) Source: CCP_Inst/C_Inst/MTBus_Address_11 (FF) Destination: CCP_Inst/C_Inst/fsmfake3_0 (FF) Requirement: 20.833ns Data Path Delay: 19.314ns (Levels of Logic = 11) Clock Path Skew: -0.058ns (0.708 - 0.766) Source Clock: CLK_in_BUFGP rising at 0.000ns Destination Clock: CLK_in_BUFGP rising at 20.833ns Clock Uncertainty: 0.035ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.070ns Total Input Jitter (TIJ): 0.002ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Maximum Data Path at Slow Process Corner: CCP_Inst/C_Inst/MTBus_Address_11 to CCP_Inst/C_Inst/fsmfake3_0 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X23Y68.CQ Tcko 0.548 CCP_Inst/C_Inst/MTBus_Address<11> CCP_Inst/C_Inst/MTBus_Address_11 SLICE_X32Y62.C3 net (fanout=18) 3.385 CCP_Inst/C_Inst/MTBus_Address<11> SLICE_X32Y62.COUT Topcyc 0.471 CCP_Inst/C_Inst/Madd_MTBus_Address[31]_GND_31_o_add_121_OUT_cy<12> CCP_Inst/C_Inst/MTBus_Address<11>_rt.1 CCP_Inst/C_Inst/Madd_MTBus_Address[31]_GND_31_o_add_121_OUT_cy<12> SLICE_X32Y63.CIN net (fanout=1) 0.003 CCP_Inst/C_Inst/Madd_MTBus_Address[31]_GND_31_o_add_121_OUT_cy<12> SLICE_X32Y63.COUT Tbyp 0.123 CCP_Inst/C_Inst/Madd_MTBus_Address[31]_GND_31_o_add_121_OUT_cy<16> CCP_Inst/C_Inst/Madd_MTBus_Address[31]_GND_31_o_add_121_OUT_cy<16> SLICE_X32Y64.CIN net (fanout=1) 0.206 CCP_Inst/C_Inst/Madd_MTBus_Address[31]_GND_31_o_add_121_OUT_cy<16> SLICE_X32Y64.COUT Tbyp 0.123 CCP_Inst/C_Inst/Madd_MTBus_Address[31]_GND_31_o_add_121_OUT_cy<20> CCP_Inst/C_Inst/Madd_MTBus_Address[31]_GND_31_o_add_121_OUT_cy<20> SLICE_X32Y65.CIN net (fanout=1) 0.003 CCP_Inst/C_Inst/Madd_MTBus_Address[31]_GND_31_o_add_121_OUT_cy<20> SLICE_X32Y65.COUT Tbyp 0.123 CCP_Inst/C_Inst/Madd_MTBus_Address[31]_GND_31_o_add_121_OUT_cy<24> CCP_Inst/C_Inst/Madd_MTBus_Address[31]_GND_31_o_add_121_OUT_cy<24> SLICE_X32Y66.CIN net (fanout=1) 0.003 CCP_Inst/C_Inst/Madd_MTBus_Address[31]_GND_31_o_add_121_OUT_cy<24> SLICE_X32Y66.AMUX Tcina 0.285 CCP_Inst/C_Inst/Madd_MTBus_Address[31]_GND_31_o_add_121_OUT_cy<28> CCP_Inst/C_Inst/Madd_MTBus_Address[31]_GND_31_o_add_121_OUT_cy<28> SLICE_X34Y61.B1 net (fanout=1) 1.710 CCP_Inst/C_Inst/MTBus_Address[31]_GND_31_o_add_121_OUT<25> SLICE_X34Y61.CMUX Topbc 0.907 CCP_Inst/C_Inst/GND_31_o_PWR_39_o_MUX_1158_o CCP_Inst/C_Inst/Mcompar_GND_31_o_MTBus_Address[31]_LessThan_123_o_lut<5> CCP_Inst/C_Inst/GND_31_o_PWR_39_o_MUX_1158_o1_cy SLICE_X27Y67.A4 net (fanout=14) 2.084 CCP_Inst/C_Inst/Mcompar_GND_31_o_MTBus_Address[31]_LessThan_123_o_cy<6> SLICE_X27Y67.A Tilo 0.341 CCP_Inst/C_Inst/N1194 CCP_Inst/C_Inst/GND_31_o_StateMachine.Step[2]_equal_142_o<2>1 SLICE_X47Y46.A6 net (fanout=44) 3.718 CCP_Inst/C_Inst/GND_31_o_StateMachine.Step[2]_equal_142_o SLICE_X47Y46.A Tilo 0.341 CCP_Inst/C_Inst/Mmux_StateMachine.Progress[2]_Task[4]_mux_482_OUT16 CCP_Inst/C_Inst/Mmux_StateMachine.Progress[2]_Task[4]_mux_482_OUT17 SLICE_X45Y46.C4 net (fanout=2) 0.580 CCP_Inst/C_Inst/Mmux_StateMachine.Progress[2]_Task[4]_mux_482_OUT16 SLICE_X45Y46.C Tilo 0.341 CCP_Inst/C_Inst/Mmux_StateMachine.Progress[2]_Task[4]_mux_482_OUT18 CCP_Inst/C_Inst/Mmux_StateMachine.Progress[2]_Task[4]_mux_482_OUT110_SW0 SLICE_X40Y54.C3 net (fanout=1) 1.776 N881 SLICE_X40Y54.C Tilo 0.333 CCP_Inst/C_Inst/StateMachine.Step_FSM_FFd5_2 CCP_Inst/C_Inst/Mmux_StateMachine.Progress[2]_Task[4]_mux_482_OUT113 SLICE_X45Y61.A4 net (fanout=11) 1.405 CCP_Inst/C_Inst/StateMachine.Progress[2]_Task[4]_mux_482_OUT<0> SLICE_X45Y61.CLK Tas 0.505 CCP_Inst/C_Inst/fsmfake3<2> CCP_Inst/C_Inst/Mmux_StateMachine.Step[2]_StateMachine.Step[2]_mux_513_OUT618 CCP_Inst/C_Inst/fsmfake3_0 ------------------------------------------------- --------------------------- Total 19.314ns (4.441ns logic, 14.873ns route) (23.0% logic, 77.0% route) -------------------------------------------------------------------------------- Slack (setup path): 1.435ns (requirement - (data path - clock path skew + uncertainty)) Source: CCP_Inst/C_Inst/MTBus_Address_11 (FF) Destination: CCP_Inst/C_Inst/fsmfake3_0 (FF) Requirement: 20.833ns Data Path Delay: 19.305ns (Levels of Logic = 12) Clock Path Skew: -0.058ns (0.708 - 0.766) Source Clock: CLK_in_BUFGP rising at 0.000ns Destination Clock: CLK_in_BUFGP rising at 20.833ns Clock Uncertainty: 0.035ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.070ns Total Input Jitter (TIJ): 0.002ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Maximum Data Path at Slow Process Corner: CCP_Inst/C_Inst/MTBus_Address_11 to CCP_Inst/C_Inst/fsmfake3_0 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X23Y68.CQ Tcko 0.548 CCP_Inst/C_Inst/MTBus_Address<11> CCP_Inst/C_Inst/MTBus_Address_11 SLICE_X32Y62.C3 net (fanout=18) 3.385 CCP_Inst/C_Inst/MTBus_Address<11> SLICE_X32Y62.COUT Topcyc 0.471 CCP_Inst/C_Inst/Madd_MTBus_Address[31]_GND_31_o_add_121_OUT_cy<12> CCP_Inst/C_Inst/MTBus_Address<11>_rt.1 CCP_Inst/C_Inst/Madd_MTBus_Address[31]_GND_31_o_add_121_OUT_cy<12> SLICE_X32Y63.CIN net (fanout=1) 0.003 CCP_Inst/C_Inst/Madd_MTBus_Address[31]_GND_31_o_add_121_OUT_cy<12> SLICE_X32Y63.COUT Tbyp 0.123 CCP_Inst/C_Inst/Madd_MTBus_Address[31]_GND_31_o_add_121_OUT_cy<16> CCP_Inst/C_Inst/Madd_MTBus_Address[31]_GND_31_o_add_121_OUT_cy<16> SLICE_X32Y64.CIN net (fanout=1) 0.206 CCP_Inst/C_Inst/Madd_MTBus_Address[31]_GND_31_o_add_121_OUT_cy<16> SLICE_X32Y64.COUT Tbyp 0.123 CCP_Inst/C_Inst/Madd_MTBus_Address[31]_GND_31_o_add_121_OUT_cy<20> CCP_Inst/C_Inst/Madd_MTBus_Address[31]_GND_31_o_add_121_OUT_cy<20> SLICE_X32Y65.CIN net (fanout=1) 0.003 CCP_Inst/C_Inst/Madd_MTBus_Address[31]_GND_31_o_add_121_OUT_cy<20> SLICE_X32Y65.COUT Tbyp 0.123 CCP_Inst/C_Inst/Madd_MTBus_Address[31]_GND_31_o_add_121_OUT_cy<24> CCP_Inst/C_Inst/Madd_MTBus_Address[31]_GND_31_o_add_121_OUT_cy<24> SLICE_X32Y66.CIN net (fanout=1) 0.003 CCP_Inst/C_Inst/Madd_MTBus_Address[31]_GND_31_o_add_121_OUT_cy<24> SLICE_X32Y66.COUT Tbyp 0.123 CCP_Inst/C_Inst/Madd_MTBus_Address[31]_GND_31_o_add_121_OUT_cy<28> CCP_Inst/C_Inst/Madd_MTBus_Address[31]_GND_31_o_add_121_OUT_cy<28> SLICE_X32Y67.CIN net (fanout=1) 0.003 CCP_Inst/C_Inst/Madd_MTBus_Address[31]_GND_31_o_add_121_OUT_cy<28> SLICE_X32Y67.CMUX Tcinc 0.434 CCP_Inst/C_Inst/MTBus_Address[31]_GND_31_o_add_121_OUT<31> CCP_Inst/C_Inst/Madd_MTBus_Address[31]_GND_31_o_add_121_OUT_xor<31> SLICE_X34Y61.C1 net (fanout=1) 1.609 CCP_Inst/C_Inst/MTBus_Address[31]_GND_31_o_add_121_OUT<31> SLICE_X34Y61.CMUX Topcc 0.608 CCP_Inst/C_Inst/GND_31_o_PWR_39_o_MUX_1158_o CCP_Inst/C_Inst/Mcompar_GND_31_o_MTBus_Address[31]_LessThan_123_o_lut<6> CCP_Inst/C_Inst/GND_31_o_PWR_39_o_MUX_1158_o1_cy SLICE_X27Y67.A4 net (fanout=14) 2.084 CCP_Inst/C_Inst/Mcompar_GND_31_o_MTBus_Address[31]_LessThan_123_o_cy<6> SLICE_X27Y67.A Tilo 0.341 CCP_Inst/C_Inst/N1194 CCP_Inst/C_Inst/GND_31_o_StateMachine.Step[2]_equal_142_o<2>1 SLICE_X47Y46.A6 net (fanout=44) 3.718 CCP_Inst/C_Inst/GND_31_o_StateMachine.Step[2]_equal_142_o SLICE_X47Y46.A Tilo 0.341 CCP_Inst/C_Inst/Mmux_StateMachine.Progress[2]_Task[4]_mux_482_OUT16 CCP_Inst/C_Inst/Mmux_StateMachine.Progress[2]_Task[4]_mux_482_OUT17 SLICE_X40Y46.A6 net (fanout=2) 0.986 CCP_Inst/C_Inst/Mmux_StateMachine.Progress[2]_Task[4]_mux_482_OUT16 SLICE_X40Y46.A Tilo 0.333 N883 CCP_Inst/C_Inst/Mmux_StateMachine.Progress[2]_Task[4]_mux_482_OUT110_SW2 SLICE_X40Y54.C1 net (fanout=1) 1.494 N883 SLICE_X40Y54.C Tilo 0.333 CCP_Inst/C_Inst/StateMachine.Step_FSM_FFd5_2 CCP_Inst/C_Inst/Mmux_StateMachine.Progress[2]_Task[4]_mux_482_OUT113 SLICE_X45Y61.A4 net (fanout=11) 1.405 CCP_Inst/C_Inst/StateMachine.Progress[2]_Task[4]_mux_482_OUT<0> SLICE_X45Y61.CLK Tas 0.505 CCP_Inst/C_Inst/fsmfake3<2> CCP_Inst/C_Inst/Mmux_StateMachine.Step[2]_StateMachine.Step[2]_mux_513_OUT618 CCP_Inst/C_Inst/fsmfake3_0 ------------------------------------------------- --------------------------- Total 19.305ns (4.406ns logic, 14.899ns route) (22.8% logic, 77.2% route) -------------------------------------------------------------------------------- Paths for end point CCP_Inst/C_Inst/StateMachine.Step_FSM_FFd5 (SLICE_X41Y54.AX), 53111 paths -------------------------------------------------------------------------------- Slack (setup path): 1.311ns (requirement - (data path - clock path skew + uncertainty)) Source: CCP_Inst/C_Inst/MTBus_Address_11 (FF) Destination: CCP_Inst/C_Inst/StateMachine.Step_FSM_FFd5 (FF) Requirement: 20.833ns Data Path Delay: 19.422ns (Levels of Logic = 11) Clock Path Skew: -0.065ns (0.701 - 0.766) Source Clock: CLK_in_BUFGP rising at 0.000ns Destination Clock: CLK_in_BUFGP rising at 20.833ns Clock Uncertainty: 0.035ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.070ns Total Input Jitter (TIJ): 0.002ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Maximum Data Path at Slow Process Corner: CCP_Inst/C_Inst/MTBus_Address_11 to CCP_Inst/C_Inst/StateMachine.Step_FSM_FFd5 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X23Y68.CQ Tcko 0.548 CCP_Inst/C_Inst/MTBus_Address<11> CCP_Inst/C_Inst/MTBus_Address_11 SLICE_X32Y62.C3 net (fanout=18) 3.385 CCP_Inst/C_Inst/MTBus_Address<11> SLICE_X32Y62.COUT Topcyc 0.471 CCP_Inst/C_Inst/Madd_MTBus_Address[31]_GND_31_o_add_121_OUT_cy<12> CCP_Inst/C_Inst/MTBus_Address<11>_rt.1 CCP_Inst/C_Inst/Madd_MTBus_Address[31]_GND_31_o_add_121_OUT_cy<12> SLICE_X32Y63.CIN net (fanout=1) 0.003 CCP_Inst/C_Inst/Madd_MTBus_Address[31]_GND_31_o_add_121_OUT_cy<12> SLICE_X32Y63.COUT Tbyp 0.123 CCP_Inst/C_Inst/Madd_MTBus_Address[31]_GND_31_o_add_121_OUT_cy<16> CCP_Inst/C_Inst/Madd_MTBus_Address[31]_GND_31_o_add_121_OUT_cy<16> SLICE_X32Y64.CIN net (fanout=1) 0.206 CCP_Inst/C_Inst/Madd_MTBus_Address[31]_GND_31_o_add_121_OUT_cy<16> SLICE_X32Y64.COUT Tbyp 0.123 CCP_Inst/C_Inst/Madd_MTBus_Address[31]_GND_31_o_add_121_OUT_cy<20> CCP_Inst/C_Inst/Madd_MTBus_Address[31]_GND_31_o_add_121_OUT_cy<20> SLICE_X32Y65.CIN net (fanout=1) 0.003 CCP_Inst/C_Inst/Madd_MTBus_Address[31]_GND_31_o_add_121_OUT_cy<20> SLICE_X32Y65.COUT Tbyp 0.123 CCP_Inst/C_Inst/Madd_MTBus_Address[31]_GND_31_o_add_121_OUT_cy<24> CCP_Inst/C_Inst/Madd_MTBus_Address[31]_GND_31_o_add_121_OUT_cy<24> SLICE_X32Y66.CIN net (fanout=1) 0.003 CCP_Inst/C_Inst/Madd_MTBus_Address[31]_GND_31_o_add_121_OUT_cy<24> SLICE_X32Y66.AMUX Tcina 0.285 CCP_Inst/C_Inst/Madd_MTBus_Address[31]_GND_31_o_add_121_OUT_cy<28> CCP_Inst/C_Inst/Madd_MTBus_Address[31]_GND_31_o_add_121_OUT_cy<28> SLICE_X34Y61.B1 net (fanout=1) 1.710 CCP_Inst/C_Inst/MTBus_Address[31]_GND_31_o_add_121_OUT<25> SLICE_X34Y61.CMUX Topbc 0.907 CCP_Inst/C_Inst/GND_31_o_PWR_39_o_MUX_1158_o CCP_Inst/C_Inst/Mcompar_GND_31_o_MTBus_Address[31]_LessThan_123_o_lut<5> CCP_Inst/C_Inst/GND_31_o_PWR_39_o_MUX_1158_o1_cy SLICE_X27Y67.A4 net (fanout=14) 2.084 CCP_Inst/C_Inst/Mcompar_GND_31_o_MTBus_Address[31]_LessThan_123_o_cy<6> SLICE_X27Y67.A Tilo 0.341 CCP_Inst/C_Inst/N1194 CCP_Inst/C_Inst/GND_31_o_StateMachine.Step[2]_equal_142_o<2>1 SLICE_X47Y46.A6 net (fanout=44) 3.718 CCP_Inst/C_Inst/GND_31_o_StateMachine.Step[2]_equal_142_o SLICE_X47Y46.A Tilo 0.341 CCP_Inst/C_Inst/Mmux_StateMachine.Progress[2]_Task[4]_mux_482_OUT16 CCP_Inst/C_Inst/Mmux_StateMachine.Progress[2]_Task[4]_mux_482_OUT17 SLICE_X40Y46.A6 net (fanout=2) 0.986 CCP_Inst/C_Inst/Mmux_StateMachine.Progress[2]_Task[4]_mux_482_OUT16 SLICE_X40Y46.A Tilo 0.333 N883 CCP_Inst/C_Inst/Mmux_StateMachine.Progress[2]_Task[4]_mux_482_OUT110_SW2 SLICE_X40Y54.C1 net (fanout=1) 1.494 N883 SLICE_X40Y54.C Tilo 0.333 CCP_Inst/C_Inst/StateMachine.Step_FSM_FFd5_2 CCP_Inst/C_Inst/Mmux_StateMachine.Progress[2]_Task[4]_mux_482_OUT113 SLICE_X40Y54.D5 net (fanout=11) 0.280 CCP_Inst/C_Inst/StateMachine.Progress[2]_Task[4]_mux_482_OUT<0> SLICE_X40Y54.D Tilo 0.333 CCP_Inst/C_Inst/StateMachine.Step_FSM_FFd5_2 CCP_Inst/C_Inst/StateMachine.Step_FSM_FFd5-In3 SLICE_X41Y54.AX net (fanout=2) 1.125 CCP_Inst/C_Inst/StateMachine.Step_FSM_FFd5-In SLICE_X41Y54.CLK Tdick 0.164 CCP_Inst/C_Inst/StateMachine.Step_FSM_FFd5 CCP_Inst/C_Inst/StateMachine.Step_FSM_FFd5 ------------------------------------------------- --------------------------- Total 19.422ns (4.425ns logic, 14.997ns route) (22.8% logic, 77.2% route) -------------------------------------------------------------------------------- Slack (setup path): 1.427ns (requirement - (data path - clock path skew + uncertainty)) Source: CCP_Inst/C_Inst/MTBus_Address_11 (FF) Destination: CCP_Inst/C_Inst/StateMachine.Step_FSM_FFd5 (FF) Requirement: 20.833ns Data Path Delay: 19.306ns (Levels of Logic = 11) Clock Path Skew: -0.065ns (0.701 - 0.766) Source Clock: CLK_in_BUFGP rising at 0.000ns Destination Clock: CLK_in_BUFGP rising at 20.833ns Clock Uncertainty: 0.035ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.070ns Total Input Jitter (TIJ): 0.002ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Maximum Data Path at Slow Process Corner: CCP_Inst/C_Inst/MTBus_Address_11 to CCP_Inst/C_Inst/StateMachine.Step_FSM_FFd5 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X23Y68.CQ Tcko 0.548 CCP_Inst/C_Inst/MTBus_Address<11> CCP_Inst/C_Inst/MTBus_Address_11 SLICE_X32Y62.C3 net (fanout=18) 3.385 CCP_Inst/C_Inst/MTBus_Address<11> SLICE_X32Y62.COUT Topcyc 0.471 CCP_Inst/C_Inst/Madd_MTBus_Address[31]_GND_31_o_add_121_OUT_cy<12> CCP_Inst/C_Inst/MTBus_Address<11>_rt.1 CCP_Inst/C_Inst/Madd_MTBus_Address[31]_GND_31_o_add_121_OUT_cy<12> SLICE_X32Y63.CIN net (fanout=1) 0.003 CCP_Inst/C_Inst/Madd_MTBus_Address[31]_GND_31_o_add_121_OUT_cy<12> SLICE_X32Y63.COUT Tbyp 0.123 CCP_Inst/C_Inst/Madd_MTBus_Address[31]_GND_31_o_add_121_OUT_cy<16> CCP_Inst/C_Inst/Madd_MTBus_Address[31]_GND_31_o_add_121_OUT_cy<16> SLICE_X32Y64.CIN net (fanout=1) 0.206 CCP_Inst/C_Inst/Madd_MTBus_Address[31]_GND_31_o_add_121_OUT_cy<16> SLICE_X32Y64.COUT Tbyp 0.123 CCP_Inst/C_Inst/Madd_MTBus_Address[31]_GND_31_o_add_121_OUT_cy<20> CCP_Inst/C_Inst/Madd_MTBus_Address[31]_GND_31_o_add_121_OUT_cy<20> SLICE_X32Y65.CIN net (fanout=1) 0.003 CCP_Inst/C_Inst/Madd_MTBus_Address[31]_GND_31_o_add_121_OUT_cy<20> SLICE_X32Y65.COUT Tbyp 0.123 CCP_Inst/C_Inst/Madd_MTBus_Address[31]_GND_31_o_add_121_OUT_cy<24> CCP_Inst/C_Inst/Madd_MTBus_Address[31]_GND_31_o_add_121_OUT_cy<24> SLICE_X32Y66.CIN net (fanout=1) 0.003 CCP_Inst/C_Inst/Madd_MTBus_Address[31]_GND_31_o_add_121_OUT_cy<24> SLICE_X32Y66.AMUX Tcina 0.285 CCP_Inst/C_Inst/Madd_MTBus_Address[31]_GND_31_o_add_121_OUT_cy<28> CCP_Inst/C_Inst/Madd_MTBus_Address[31]_GND_31_o_add_121_OUT_cy<28> SLICE_X34Y61.B1 net (fanout=1) 1.710 CCP_Inst/C_Inst/MTBus_Address[31]_GND_31_o_add_121_OUT<25> SLICE_X34Y61.CMUX Topbc 0.907 CCP_Inst/C_Inst/GND_31_o_PWR_39_o_MUX_1158_o CCP_Inst/C_Inst/Mcompar_GND_31_o_MTBus_Address[31]_LessThan_123_o_lut<5> CCP_Inst/C_Inst/GND_31_o_PWR_39_o_MUX_1158_o1_cy SLICE_X27Y67.A4 net (fanout=14) 2.084 CCP_Inst/C_Inst/Mcompar_GND_31_o_MTBus_Address[31]_LessThan_123_o_cy<6> SLICE_X27Y67.A Tilo 0.341 CCP_Inst/C_Inst/N1194 CCP_Inst/C_Inst/GND_31_o_StateMachine.Step[2]_equal_142_o<2>1 SLICE_X47Y46.A6 net (fanout=44) 3.718 CCP_Inst/C_Inst/GND_31_o_StateMachine.Step[2]_equal_142_o SLICE_X47Y46.A Tilo 0.341 CCP_Inst/C_Inst/Mmux_StateMachine.Progress[2]_Task[4]_mux_482_OUT16 CCP_Inst/C_Inst/Mmux_StateMachine.Progress[2]_Task[4]_mux_482_OUT17 SLICE_X45Y46.C4 net (fanout=2) 0.580 CCP_Inst/C_Inst/Mmux_StateMachine.Progress[2]_Task[4]_mux_482_OUT16 SLICE_X45Y46.C Tilo 0.341 CCP_Inst/C_Inst/Mmux_StateMachine.Progress[2]_Task[4]_mux_482_OUT18 CCP_Inst/C_Inst/Mmux_StateMachine.Progress[2]_Task[4]_mux_482_OUT110_SW0 SLICE_X40Y54.C3 net (fanout=1) 1.776 N881 SLICE_X40Y54.C Tilo 0.333 CCP_Inst/C_Inst/StateMachine.Step_FSM_FFd5_2 CCP_Inst/C_Inst/Mmux_StateMachine.Progress[2]_Task[4]_mux_482_OUT113 SLICE_X40Y54.D5 net (fanout=11) 0.280 CCP_Inst/C_Inst/StateMachine.Progress[2]_Task[4]_mux_482_OUT<0> SLICE_X40Y54.D Tilo 0.333 CCP_Inst/C_Inst/StateMachine.Step_FSM_FFd5_2 CCP_Inst/C_Inst/StateMachine.Step_FSM_FFd5-In3 SLICE_X41Y54.AX net (fanout=2) 1.125 CCP_Inst/C_Inst/StateMachine.Step_FSM_FFd5-In SLICE_X41Y54.CLK Tdick 0.164 CCP_Inst/C_Inst/StateMachine.Step_FSM_FFd5 CCP_Inst/C_Inst/StateMachine.Step_FSM_FFd5 ------------------------------------------------- --------------------------- Total 19.306ns (4.433ns logic, 14.873ns route) (23.0% logic, 77.0% route) -------------------------------------------------------------------------------- Slack (setup path): 1.436ns (requirement - (data path - clock path skew + uncertainty)) Source: CCP_Inst/C_Inst/MTBus_Address_11 (FF) Destination: CCP_Inst/C_Inst/StateMachine.Step_FSM_FFd5 (FF) Requirement: 20.833ns Data Path Delay: 19.297ns (Levels of Logic = 12) Clock Path Skew: -0.065ns (0.701 - 0.766) Source Clock: CLK_in_BUFGP rising at 0.000ns Destination Clock: CLK_in_BUFGP rising at 20.833ns Clock Uncertainty: 0.035ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.070ns Total Input Jitter (TIJ): 0.002ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Maximum Data Path at Slow Process Corner: CCP_Inst/C_Inst/MTBus_Address_11 to CCP_Inst/C_Inst/StateMachine.Step_FSM_FFd5 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X23Y68.CQ Tcko 0.548 CCP_Inst/C_Inst/MTBus_Address<11> CCP_Inst/C_Inst/MTBus_Address_11 SLICE_X32Y62.C3 net (fanout=18) 3.385 CCP_Inst/C_Inst/MTBus_Address<11> SLICE_X32Y62.COUT Topcyc 0.471 CCP_Inst/C_Inst/Madd_MTBus_Address[31]_GND_31_o_add_121_OUT_cy<12> CCP_Inst/C_Inst/MTBus_Address<11>_rt.1 CCP_Inst/C_Inst/Madd_MTBus_Address[31]_GND_31_o_add_121_OUT_cy<12> SLICE_X32Y63.CIN net (fanout=1) 0.003 CCP_Inst/C_Inst/Madd_MTBus_Address[31]_GND_31_o_add_121_OUT_cy<12> SLICE_X32Y63.COUT Tbyp 0.123 CCP_Inst/C_Inst/Madd_MTBus_Address[31]_GND_31_o_add_121_OUT_cy<16> CCP_Inst/C_Inst/Madd_MTBus_Address[31]_GND_31_o_add_121_OUT_cy<16> SLICE_X32Y64.CIN net (fanout=1) 0.206 CCP_Inst/C_Inst/Madd_MTBus_Address[31]_GND_31_o_add_121_OUT_cy<16> SLICE_X32Y64.COUT Tbyp 0.123 CCP_Inst/C_Inst/Madd_MTBus_Address[31]_GND_31_o_add_121_OUT_cy<20> CCP_Inst/C_Inst/Madd_MTBus_Address[31]_GND_31_o_add_121_OUT_cy<20> SLICE_X32Y65.CIN net (fanout=1) 0.003 CCP_Inst/C_Inst/Madd_MTBus_Address[31]_GND_31_o_add_121_OUT_cy<20> SLICE_X32Y65.COUT Tbyp 0.123 CCP_Inst/C_Inst/Madd_MTBus_Address[31]_GND_31_o_add_121_OUT_cy<24> CCP_Inst/C_Inst/Madd_MTBus_Address[31]_GND_31_o_add_121_OUT_cy<24> SLICE_X32Y66.CIN net (fanout=1) 0.003 CCP_Inst/C_Inst/Madd_MTBus_Address[31]_GND_31_o_add_121_OUT_cy<24> SLICE_X32Y66.COUT Tbyp 0.123 CCP_Inst/C_Inst/Madd_MTBus_Address[31]_GND_31_o_add_121_OUT_cy<28> CCP_Inst/C_Inst/Madd_MTBus_Address[31]_GND_31_o_add_121_OUT_cy<28> SLICE_X32Y67.CIN net (fanout=1) 0.003 CCP_Inst/C_Inst/Madd_MTBus_Address[31]_GND_31_o_add_121_OUT_cy<28> SLICE_X32Y67.CMUX Tcinc 0.434 CCP_Inst/C_Inst/MTBus_Address[31]_GND_31_o_add_121_OUT<31> CCP_Inst/C_Inst/Madd_MTBus_Address[31]_GND_31_o_add_121_OUT_xor<31> SLICE_X34Y61.C1 net (fanout=1) 1.609 CCP_Inst/C_Inst/MTBus_Address[31]_GND_31_o_add_121_OUT<31> SLICE_X34Y61.CMUX Topcc 0.608 CCP_Inst/C_Inst/GND_31_o_PWR_39_o_MUX_1158_o CCP_Inst/C_Inst/Mcompar_GND_31_o_MTBus_Address[31]_LessThan_123_o_lut<6> CCP_Inst/C_Inst/GND_31_o_PWR_39_o_MUX_1158_o1_cy SLICE_X27Y67.A4 net (fanout=14) 2.084 CCP_Inst/C_Inst/Mcompar_GND_31_o_MTBus_Address[31]_LessThan_123_o_cy<6> SLICE_X27Y67.A Tilo 0.341 CCP_Inst/C_Inst/N1194 CCP_Inst/C_Inst/GND_31_o_StateMachine.Step[2]_equal_142_o<2>1 SLICE_X47Y46.A6 net (fanout=44) 3.718 CCP_Inst/C_Inst/GND_31_o_StateMachine.Step[2]_equal_142_o SLICE_X47Y46.A Tilo 0.341 CCP_Inst/C_Inst/Mmux_StateMachine.Progress[2]_Task[4]_mux_482_OUT16 CCP_Inst/C_Inst/Mmux_StateMachine.Progress[2]_Task[4]_mux_482_OUT17 SLICE_X40Y46.A6 net (fanout=2) 0.986 CCP_Inst/C_Inst/Mmux_StateMachine.Progress[2]_Task[4]_mux_482_OUT16 SLICE_X40Y46.A Tilo 0.333 N883 CCP_Inst/C_Inst/Mmux_StateMachine.Progress[2]_Task[4]_mux_482_OUT110_SW2 SLICE_X40Y54.C1 net (fanout=1) 1.494 N883 SLICE_X40Y54.C Tilo 0.333 CCP_Inst/C_Inst/StateMachine.Step_FSM_FFd5_2 CCP_Inst/C_Inst/Mmux_StateMachine.Progress[2]_Task[4]_mux_482_OUT113 SLICE_X40Y54.D5 net (fanout=11) 0.280 CCP_Inst/C_Inst/StateMachine.Progress[2]_Task[4]_mux_482_OUT<0> SLICE_X40Y54.D Tilo 0.333 CCP_Inst/C_Inst/StateMachine.Step_FSM_FFd5_2 CCP_Inst/C_Inst/StateMachine.Step_FSM_FFd5-In3 SLICE_X41Y54.AX net (fanout=2) 1.125 CCP_Inst/C_Inst/StateMachine.Step_FSM_FFd5-In SLICE_X41Y54.CLK Tdick 0.164 CCP_Inst/C_Inst/StateMachine.Step_FSM_FFd5 CCP_Inst/C_Inst/StateMachine.Step_FSM_FFd5 ------------------------------------------------- --------------------------- Total 19.297ns (4.398ns logic, 14.899ns route) (22.8% logic, 77.2% route) -------------------------------------------------------------------------------- Hold Paths: TS_CLK_in = PERIOD TIMEGRP "CLK_in" 48 MHz HIGH 50% INPUT_JITTER 0.0021 ns; -------------------------------------------------------------------------------- Paths for end point U_ila_pro_0/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[24].I_SRLT_NE_0.DLY9/SRL16E (SLICE_X14Y91.AI), 1 path -------------------------------------------------------------------------------- Slack (hold path): 0.248ns (requirement - (clock path skew + uncertainty - data path)) Source: U_ila_pro_0/U0/I_DQ.G_DW[24].U_DQ (FF) Destination: U_ila_pro_0/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[24].I_SRLT_NE_0.DLY9/SRL16E (FF) Requirement: 0.000ns Data Path Delay: 0.250ns (Levels of Logic = 0) Clock Path Skew: 0.002ns (0.039 - 0.037) Source Clock: CLK_in_BUFGP rising at 0.000ns Destination Clock: CLK_in_BUFGP rising at 20.833ns Clock Uncertainty: 0.000ns Minimum Data Path at Fast Process Corner: U_ila_pro_0/U0/I_DQ.G_DW[24].U_DQ to U_ila_pro_0/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[24].I_SRLT_NE_0.DLY9/SRL16E Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X15Y91.AQ Tcko 0.198 U_ila_pro_0/U0/iDATA<27> U_ila_pro_0/U0/I_DQ.G_DW[24].U_DQ SLICE_X14Y91.AI net (fanout=1) 0.022 U_ila_pro_0/U0/iDATA<24> SLICE_X14Y91.CLK Tdh (-Th) -0.030 U_ila_pro_0/U0/I_YES_D.U_ILA/iDATA<27> U_ila_pro_0/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[24].I_SRLT_NE_0.DLY9/SRL16E ------------------------------------------------- --------------------------- Total 0.250ns (0.228ns logic, 0.022ns route) (91.2% logic, 8.8% route) -------------------------------------------------------------------------------- Paths for end point U_ila_pro_0/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[36].I_SRLT_NE_0.DLY9/SRL16E (SLICE_X22Y12.AI), 1 path -------------------------------------------------------------------------------- Slack (hold path): 0.248ns (requirement - (clock path skew + uncertainty - data path)) Source: U_ila_pro_0/U0/I_DQ.G_DW[36].U_DQ (FF) Destination: U_ila_pro_0/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[36].I_SRLT_NE_0.DLY9/SRL16E (FF) Requirement: 0.000ns Data Path Delay: 0.250ns (Levels of Logic = 0) Clock Path Skew: 0.002ns (0.041 - 0.039) Source Clock: CLK_in_BUFGP rising at 0.000ns Destination Clock: CLK_in_BUFGP rising at 20.833ns Clock Uncertainty: 0.000ns Minimum Data Path at Fast Process Corner: U_ila_pro_0/U0/I_DQ.G_DW[36].U_DQ to U_ila_pro_0/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[36].I_SRLT_NE_0.DLY9/SRL16E Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X23Y12.AQ Tcko 0.198 U_ila_pro_0/U0/iDATA<39> U_ila_pro_0/U0/I_DQ.G_DW[36].U_DQ SLICE_X22Y12.AI net (fanout=1) 0.022 U_ila_pro_0/U0/iDATA<36> SLICE_X22Y12.CLK Tdh (-Th) -0.030 U_ila_pro_0/U0/I_YES_D.U_ILA/iDATA<39> U_ila_pro_0/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[36].I_SRLT_NE_0.DLY9/SRL16E ------------------------------------------------- --------------------------- Total 0.250ns (0.228ns logic, 0.022ns route) (91.2% logic, 8.8% route) -------------------------------------------------------------------------------- Paths for end point U_ila_pro_0/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[28].I_SRLT_NE_0.DLY9/SRL16E (SLICE_X26Y76.AI), 1 path -------------------------------------------------------------------------------- Slack (hold path): 0.248ns (requirement - (clock path skew + uncertainty - data path)) Source: U_ila_pro_0/U0/I_DQ.G_DW[28].U_DQ (FF) Destination: U_ila_pro_0/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[28].I_SRLT_NE_0.DLY9/SRL16E (FF) Requirement: 0.000ns Data Path Delay: 0.250ns (Levels of Logic = 0) Clock Path Skew: 0.002ns (0.041 - 0.039) Source Clock: CLK_in_BUFGP rising at 0.000ns Destination Clock: CLK_in_BUFGP rising at 20.833ns Clock Uncertainty: 0.000ns Minimum Data Path at Fast Process Corner: U_ila_pro_0/U0/I_DQ.G_DW[28].U_DQ to U_ila_pro_0/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[28].I_SRLT_NE_0.DLY9/SRL16E Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X27Y76.AQ Tcko 0.198 U_ila_pro_0/U0/iDATA<31> U_ila_pro_0/U0/I_DQ.G_DW[28].U_DQ SLICE_X26Y76.AI net (fanout=1) 0.022 U_ila_pro_0/U0/iDATA<28> SLICE_X26Y76.CLK Tdh (-Th) -0.030 U_ila_pro_0/U0/I_YES_D.U_ILA/iDATA<31> U_ila_pro_0/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[28].I_SRLT_NE_0.DLY9/SRL16E ------------------------------------------------- --------------------------- Total 0.250ns (0.228ns logic, 0.022ns route) (91.2% logic, 8.8% route) -------------------------------------------------------------------------------- Component Switching Limit Checks: TS_CLK_in = PERIOD TIMEGRP "CLK_in" 48 MHz HIGH 50% INPUT_JITTER 0.0021 ns; -------------------------------------------------------------------------------- Slack: 16.988ns (period - min period limit) Period: 20.833ns Min period limit: 3.845ns (260.078MHz) (Trper_CLKB(Fmax)) Physical resource: U_ila_pro_0/U0/I_YES_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_S6.U_CS_BRAM_CASCADE_S6/I_DEPTH_EQ_24K_OR_32K.U_SBRAM_0/I_B18KGT0.G_RAMB18[38].u_ramb18/U_RAMB18/CLKB Logical resource: U_ila_pro_0/U0/I_YES_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_S6.U_CS_BRAM_CASCADE_S6/I_DEPTH_EQ_24K_OR_32K.U_SBRAM_0/I_B18KGT0.G_RAMB18[38].u_ramb18/U_RAMB18/CLKB Location pin: RAMB16_X2Y2.CLKB Clock network: CLK_in_BUFGP -------------------------------------------------------------------------------- Slack: 16.988ns (period - min period limit) Period: 20.833ns Min period limit: 3.845ns (260.078MHz) (Trper_CLKB(Fmax)) Physical resource: U_ila_pro_0/U0/I_YES_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_S6.U_CS_BRAM_CASCADE_S6/I_DEPTH_EQ_24K_OR_32K.U_SBRAM_1/I_B18KGT0.G_RAMB18[38].u_ramb18/U_RAMB18/CLKB Logical resource: U_ila_pro_0/U0/I_YES_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_S6.U_CS_BRAM_CASCADE_S6/I_DEPTH_EQ_24K_OR_32K.U_SBRAM_1/I_B18KGT0.G_RAMB18[38].u_ramb18/U_RAMB18/CLKB Location pin: RAMB16_X2Y8.CLKB Clock network: CLK_in_BUFGP -------------------------------------------------------------------------------- Slack: 16.988ns (period - min period limit) Period: 20.833ns Min period limit: 3.845ns (260.078MHz) (Trper_CLKB(Fmax)) Physical resource: U_ila_pro_0/U0/I_YES_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_S6.U_CS_BRAM_CASCADE_S6/I_DEPTH_EQ_24K_OR_32K.U_SBRAM_0/I_B18KGT0.G_RAMB18[41].u_ramb18/U_RAMB18/CLKB Logical resource: U_ila_pro_0/U0/I_YES_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_S6.U_CS_BRAM_CASCADE_S6/I_DEPTH_EQ_24K_OR_32K.U_SBRAM_0/I_B18KGT0.G_RAMB18[41].u_ramb18/U_RAMB18/CLKB Location pin: RAMB16_X1Y12.CLKB Clock network: CLK_in_BUFGP -------------------------------------------------------------------------------- All constraints were met. Data Sheet report: ----------------- All values displayed in nanoseconds (ns) Clock to Setup on destination clock CLK_in ---------------+---------+---------+---------+---------+ | Src:Rise| Src:Fall| Src:Rise| Src:Fall| Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| ---------------+---------+---------+---------+---------+ CLK_in | 19.557| | | | ---------------+---------+---------+---------+---------+ Timing summary: --------------- Timing errors: 0 Score: 0 (Setup/Max: 0, Hold: 0) Constraints cover 7386295 paths, 0 nets, and 35673 connections Design statistics: Minimum period: 19.557ns{1} (Maximum frequency: 51.133MHz) Maximum path delay from/to any node: 5.620ns ------------------------------------Footnotes----------------------------------- 1) The minimum period statistic assumes all single cycle delays. Analysis completed Wed Mar 02 20:44:20 2011 --------------------------------------------------------------------------------