sysclk.h
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00038 #ifndef CHIP_SYSCLK_H_INCLUDED
00039 #define CHIP_SYSCLK_H_INCLUDED
00040
00041 #ifdef __cplusplus
00042 extern "C" {
00043 #endif
00044
00045 #define FCPU_HZ_MISTRAL 20000000
00046 #define FCPU_HZ_ZEPHYR 48000000
00047
00048 #define FCPU_HZ FCPU_HZ_ZEPHYR
00049 #define FPBA_HZ FCPU_HZ
00050
00056
00057
00058 #define SYSCLK_SRC_RCSYS 0 //!< Use slow clock as main clock
00059 #define SYSCLK_SRC_OSC0 1 //!< Use OSC0 as main clock
00060 #define SYSCLK_SRC_PLL0 2 //!< Use PLL0 as main clock
00061 #define SYSCLK_SRC_ZEPHYR_CLOCK 3 //!< Use Zephyr hardcoded clock
00062
00063
00065
00066 #define USBCLK_SRC_OSC0 0 //!< Use OSC0
00067 #define USBCLK_SRC_PLL0 1 //!< Use PLL0
00068 #define USBCLK_SRC_PLL1 2 //!< Use PLL1
00069
00070
00071
00073
00074 #define SYSCLK_OCD AVR32_OCD_CLK_CPU //!< On-Chip Debug system
00075 #define SYSCLK_SYSTIMER AVR32_CORE_CLK_CPU_COUNT //!< COUNT/COMPARE registers
00076
00077
00079
00080
00081 #define SYSCLK_FLASHC_DATA (AVR32_FLASHC_CLK_HSB % 32)
00082
00083 #define SYSCLK_PBA_BRIDGE (AVR32_HMATRIX_CLK_HSB_PBA_BRIDGE % 32)
00084
00085 #define SYSCLK_PBB_BRIDGE (AVR32_HMATRIX_CLK_HSB_PBB_BRIDGE % 32)
00086
00087 #define SYSCLK_USBC_DATA (AVR32_USBC_CLK_HSB % 32)
00088
00089 #define SYSCLK_MACB_DATA (AVR32_MACB_CLK_HSB % 32)
00090
00091 #define SYSCLK_PDCA_HSB (AVR32_PDCA_CLK_HSB % 32)
00092
00093 #define SYSCLK_EBI (AVR32_EBI_CLK_HSB % 32)
00094
00095
00097
00098
00099 #define SYSCLK_INTC (AVR32_INTC_CLK_PBA % 32)
00100
00101 #define SYSCLK_GPIO (AVR32_GPIO_CLK_PBA % 32)
00102
00103 #define SYSCLK_PDCA_PB (AVR32_PDCA_CLK_PBA % 32)
00104
00105 #define SYSCLK_PM (AVR32_PM_CLK_PBA % 32)
00106
00107 #define SYSCLK_ADC (AVR32_ADC_CLK_PBA % 32)
00108
00109 #define SYSCLK_SPI0 (AVR32_SPI0_CLK_PBA % 32)
00110
00111 #define SYSCLK_SPI1 (AVR32_SPI1_CLK_PBA % 32)
00112
00113 #define SYSCLK_TWI (AVR32_TWI_CLK_PBA % 32)
00114
00115 #define SYSCLK_USART0 (AVR32_USART0_CLK_PBA % 32)
00116
00117 #define SYSCLK_USART1 (AVR32_USART1_CLK_PBA % 32)
00118
00119 #define SYSCLK_USART2 (AVR32_USART2_CLK_PBA % 32)
00120
00121 #define SYSCLK_USART3 (AVR32_USART3_CLK_PBA % 32)
00122
00123 #define SYSCLK_PWM (AVR32_PWM_CLK_PBA % 32)
00124
00125 #define SYSCLK_SSC (AVR32_SSC_CLK_PBA % 32)
00126
00127 #define SYSCLK_TC (AVR32_TC_CLK_PBA % 32)
00128
00129 #define SYSCLK_DAC (AVR32_ABDAC_CLK_PBA % 32)
00130
00131
00133
00134
00135 #define SYSCLK_HMATRIX (AVR32_HMATRIX_CLK_PBB % 32)
00136
00137 #define SYSCLK_USBC_REGS (AVR32_USBC_CLK_PBB % 32)
00138
00139 #define SYSCLK_FLASHC_REGS (AVR32_FLASHC_CLK_PBB % 32)
00140
00141 #define SYSCLK_MACB_REGS (AVR32_MACB_CLK_PBB % 32)
00142
00143 #define SYSCLK_SMC_REGS (AVR32_SMC_CLK_PBB % 32)
00144
00145 #define SYSCLK_SDRAMC_REGS (AVR32_SDRAMC_CLK_PBB % 32)
00146
00147
00148 #ifndef __ASSEMBLY__
00149
00150 #include <avr32/io.h>
00151
00152
00153 #ifndef CONFIG_SYSCLK_SOURCE
00154 # define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_RCSYS
00155 #endif
00156
00166 #ifndef CONFIG_SYSCLK_CPU_DIV
00167 # define CONFIG_SYSCLK_CPU_DIV 0
00168 #endif
00169
00179 #ifndef CONFIG_SYSCLK_PBA_DIV
00180 # define CONFIG_SYSCLK_PBA_DIV 0
00181 #endif
00182
00194
00205 static inline uint32_t sysclk_get_main_hz(void)
00206 {
00207 switch (CONFIG_SYSCLK_SOURCE) {
00208 case SYSCLK_SRC_ZEPHYR_CLOCK:
00209 return FCPU_HZ_ZEPHYR;
00210
00211 #ifdef BOARD_OSC0_HZ
00212 case SYSCLK_SRC_OSC0:
00213 return BOARD_OSC0_HZ;
00214 #endif
00215
00216 #ifdef CONFIG_PLL0_SOURCE
00217 case SYSCLK_SRC_PLL0:
00218 return pll_get_default_rate(0);
00219 #endif
00220
00221 default:
00222
00223 return 0;
00224 }
00225 }
00226
00236 static inline uint32_t sysclk_get_cpu_hz(void)
00237 {
00238 return sysclk_get_main_hz() >> CONFIG_SYSCLK_CPU_DIV;
00239 }
00240
00244 static inline uint32_t sysclk_get_hsb_hz(void)
00245 {
00246 return sysclk_get_main_hz() >> CONFIG_SYSCLK_CPU_DIV;
00247 }
00248
00252 static inline uint32_t sysclk_get_pba_hz(void)
00253 {
00254 return sysclk_get_main_hz() >> CONFIG_SYSCLK_PBA_DIV;
00255 }
00256
00260 static inline uint32_t sysclk_get_pbb_hz(void)
00261 {
00262 return sysclk_get_main_hz() >> CONFIG_SYSCLK_CPU_DIV;
00263 }
00264
00266
00267 extern void sysclk_priv_enable_module(unsigned int bus_id,
00268 unsigned int module_index);
00269 extern void sysclk_priv_disable_module(unsigned int bus_id,
00270 unsigned int module_index);
00271
00273
00274
00279 static inline void sysclk_enable_cpu_module(unsigned int index)
00280 {
00281 sysclk_priv_enable_module(AVR32_PM_CLK_GRP_CPU, index);
00282 }
00283
00288 static inline void sysclk_disable_cpu_module(unsigned int index)
00289 {
00290 sysclk_priv_disable_module(AVR32_PM_CLK_GRP_CPU, index);
00291 }
00292
00297 static inline void sysclk_enable_hsb_module(unsigned int index)
00298 {
00299 sysclk_priv_enable_module(AVR32_PM_CLK_GRP_HSB, index);
00300 }
00301
00306 static inline void sysclk_disable_hsb_module(unsigned int index)
00307 {
00308 sysclk_priv_disable_module(AVR32_PM_CLK_GRP_HSB, index);
00309 }
00310
00315 static inline void sysclk_enable_pba_module(unsigned int index)
00316 {
00317 sysclk_priv_enable_module(AVR32_PM_CLK_GRP_PBA, index);
00318 }
00319
00324 static inline void sysclk_disable_pba_module(unsigned int index)
00325 {
00326 sysclk_priv_disable_module(AVR32_PM_CLK_GRP_PBA, index);
00327 }
00328
00329 extern void sysclk_enable_pbb_module(unsigned int index);
00330 extern void sysclk_disable_pbb_module(unsigned int index);
00331
00333
00335
00336
00349 static inline void sysclk_set_prescalers(unsigned int cpu_shift,
00350 unsigned int pba_shift, unsigned int pbb_shift)
00351 {
00352 uint32_t cksel = 0;
00353
00354 Assert(cpu_shift <= pba_shift);
00355 Assert(cpu_shift <= pbb_shift);
00356
00357 if (cpu_shift > 0)
00358 cksel = ((cpu_shift - 1) << AVR32_PM_CKSEL_CPUSEL)
00359 | (1U << AVR32_PM_CKSEL_CPUDIV);
00360
00361 if (pba_shift > 0)
00362 cksel |= ((pba_shift - 1) << AVR32_PM_CKSEL_PBASEL)
00363 | (1U << AVR32_PM_CKSEL_PBADIV);
00364
00365 if (pbb_shift > 0)
00366 cksel |= ((pbb_shift - 1) << AVR32_PM_CKSEL_PBBSEL)
00367 | (1U << AVR32_PM_CKSEL_PBBDIV);
00368
00369 AVR32_PM.cksel = cksel;
00370 }
00371
00380 static inline void sysclk_set_source(uint_fast8_t src)
00381 {
00382 irqflags_t flags;
00383 uint32_t mcctrl;
00384
00385 Assert(src <= SYSCLK_SRC_PLL0);
00386
00387 flags = cpu_irq_save();
00388 mcctrl = AVR32_PM.mcctrl & ~AVR32_PM_MCCTRL_MCSEL_MASK;
00389 mcctrl |= src << AVR32_PM_MCCTRL_MCSEL;
00390 AVR32_PM.mcctrl = mcctrl;
00391 cpu_irq_restore(flags);
00392 }
00393
00395
00400 extern void sysclk_enable_usb(void);
00401
00405 extern void sysclk_disable_usb(void);
00406
00407 extern void sysclk_init(void);
00408
00409 #endif
00410
00412
00413 #ifdef __cplusplus
00414 }
00415 #endif
00416
00417 #endif