Xmega Application Note


Generic Clock Management
[Clock Management]

Collaboration diagram for Generic Clock Management:

Data Structures

struct  genclk_config
 Hardware representation of a set of generic clock parameters. More...

Enumerations

enum  genclk_source { GENCLK_SRC_OSC0 = 0, GENCLK_SRC_OSC1 = 1, GENCLK_SRC_PLL0 = 2, GENCLK_SRC_PLL1 = 3 }
 

Generic clock source ID.

More...

Generic clock configuration



static void genclk_config_defaults (struct genclk_config *cfg, unsigned int id)
 Initialize cfg to the default configuration for the clock identified by id.
static void genclk_config_read (struct genclk_config *cfg, unsigned int id)
 Read the currently active configuration of the clock identified by id into cfg.
static void genclk_config_set_divider (struct genclk_config *cfg, unsigned int divider)
 Set a new divider in configuration cfg.
static void genclk_config_set_source (struct genclk_config *cfg, enum genclk_source src)
 Select a new source clock src in configuration cfg.
static void genclk_config_write (const struct genclk_config *cfg, unsigned int id)
 Activate the configuration cfg on the clock identified by id.

Enabling and disabling Generic Clocks



static void genclk_disable (unsigned int id)
 Disable the generic clock identified by id.
static void genclk_enable (const struct genclk_config *cfg, unsigned int id)
 Activate the configuration cfg on the clock identified by id and enable it.

Chip-specific generic clock definitions



#define GENCLK_DIV_MAX   ((1 << AVR32_PM_GCCTRL_DIV_SIZE) * 2)
 Maximum divider supported by the generic clock implementation.

Detailed Description

Generic clocks are configurable clocks which run outside the system clock domain. They are often connected to peripherals which have an asynchronous component running independently of the bus clock, e.g. USB controllers, low-power timers and RTCs, etc.

Note that not all platforms have support for generic clocks; on such platforms, this API will not be available.


Define Documentation

#define GENCLK_DIV_MAX   ((1 << AVR32_PM_GCCTRL_DIV_SIZE) * 2)

Maximum divider supported by the generic clock implementation.

The max division factor applicable to the source clock of the generic clock.

Definition at line 50 of file genclk.h.

Referenced by genclk_config_set_divider().


Enumeration Type Documentation

Generic clock source ID.

Each generic clock may be generated from a different clock source. These are the available alternatives provided by the chip.

Enumerator:
GENCLK_SRC_OSC0 

Oscillator 0.

GENCLK_SRC_OSC1 

Oscillator 1.

GENCLK_SRC_PLL0 

PLL 0.

GENCLK_SRC_PLL1 

PLL 1.

Definition at line 57 of file genclk.h.

00057                    {
00058         GENCLK_SRC_OSC0    = 0,    
00059         GENCLK_SRC_OSC1    = 1,    
00060         GENCLK_SRC_PLL0    = 2,    
00061         GENCLK_SRC_PLL1    = 3,    
00062 };


Function Documentation

void genclk_config_defaults ( struct genclk_config cfg,
unsigned int  id 
) [inline, static]

Initialize cfg to the default configuration for the clock identified by id.

Definition at line 70 of file genclk.h.

References genclk_config::ctrl.

00072 {
00073         cfg->ctrl = 0;
00074 }

void genclk_config_read ( struct genclk_config cfg,
unsigned int  id 
) [inline, static]

Read the currently active configuration of the clock identified by id into cfg.

Definition at line 76 of file genclk.h.

References genclk_config::ctrl.

00078 {
00079         cfg->ctrl = AVR32_PM.gcctrl[id];
00080 }

void genclk_config_set_divider ( struct genclk_config cfg,
unsigned int  divider 
) [inline, static]

Set a new divider in configuration cfg.

Definition at line 99 of file genclk.h.

References Assert, genclk_config::ctrl, and GENCLK_DIV_MAX.

00101 {
00102         Assert(divider > 0 && divider <= GENCLK_DIV_MAX);
00103 
00104         /* Clear all the bits we're about to modify */
00105         cfg->ctrl &= ~(AVR32_PM_GCCTRL_DIVEN_MASK | AVR32_PM_GCCTRL_DIV_MASK);
00106 
00107         if (divider > 1) {
00108                 cfg->ctrl |= 1U << AVR32_PM_GCCTRL_DIVEN;
00109                 cfg->ctrl |= ((divider >> 1) - 1) << AVR32_PM_GCCTRL_DIV;
00110         }
00111 }

void genclk_config_set_source ( struct genclk_config cfg,
enum genclk_source  src 
) [inline, static]

Select a new source clock src in configuration cfg.

Definition at line 88 of file genclk.h.

References Assert, and genclk_config::ctrl.

00090 {
00091         uint32_t mask;
00092 
00093         mask = AVR32_PM_GCCTRL_OSCSEL_MASK | AVR32_PM_GCCTRL_PLLSEL_MASK;
00094         Assert(!(src & ~mask));
00095 
00096         cfg->ctrl = (cfg->ctrl & ~mask) | (src << AVR32_PM_GCCTRL_OSCSEL);
00097 }

void genclk_config_write ( const struct genclk_config cfg,
unsigned int  id 
) [inline, static]

Activate the configuration cfg on the clock identified by id.

Definition at line 82 of file genclk.h.

References genclk_config::ctrl.

00084 {
00085         AVR32_PM.gcctrl[id] = cfg->ctrl;
00086 }

void genclk_disable ( unsigned int  id  )  [inline, static]

Disable the generic clock identified by id.

Definition at line 119 of file genclk.h.

00120 {
00121         AVR32_PM.gcctrl[id] = 0;
00122 }

void genclk_enable ( const struct genclk_config cfg,
unsigned int  id 
) [inline, static]

Activate the configuration cfg on the clock identified by id and enable it.

Definition at line 113 of file genclk.h.

References genclk_config::ctrl.

00115 {
00116         AVR32_PM.gcctrl[id] = cfg->ctrl | (1U << AVR32_PM_GCCTRL_CEN);
00117 }

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