Xmega Application Note


interrupt_avr32.h

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00001 
00038 #ifndef UTILS_INTERRUPT_INTERRUPT_H
00039 #define UTILS_INTERRUPT_INTERRUPT_H
00040 
00041 #include <compiler.h>
00042 #include <preprocessor/tpaste.h>
00043 
00055 #if defined(__GNUC__) || defined(__DOXYGEN__)
00056 #  include <intc.h>
00057 
00090 #  define ISR(func, int_grp, int_lvl)    \
00091         __attribute__((__interrupt__)) static void func (void)
00092 
00104 #  define irq_initialize_vectors()    INTC_init_interrupts()
00105 
00130 #  define irq_register_handler(func, int_num, int_lvl)                         \
00131         INTC_register_interrupt(&func, int_num,                                \
00132                         TPASTE2(AVR32_INTC_INT, int_lvl))
00133 
00134 #elif defined(__ICCAVR32__)
00135 #  define ISR0(...) _Pragma(#__VA_ARGS__)
00136 #  define ISR(func, int_grp, int_lvl)                                          \
00137                 ISR0(handler=int_grp, int_lvl)                                 \
00138                 __interrupt static void func (void)
00139 #  define irq_initialize_vectors()                        do{ } while(0)
00140 #  define irq_register_handler(func, int_num, int_lvl)    do{ } while(0)
00141 #endif
00142 
00144 
00145 #if (defined __GNUC__)
00146 #  define cpu_irq_enable()                             \
00147         do {                                           \
00148                 barrier();                             \
00149                 __builtin_csrf(AVR32_SR_GM_OFFSET);    \
00150         } while (0)
00151 #  define cpu_irq_disable()                            \
00152         do {                                           \
00153                 __builtin_ssrf(AVR32_SR_GM_OFFSET);    \
00154                 barrier();                             \
00155         } while (0)
00156 #elif (defined __ICCAVR32__)
00157 #  define cpu_irq_enable()     __enable_interrupt()
00158 #  define cpu_irq_disable()    __disable_interrupt()
00159 #endif
00160 
00161 typedef uint32_t irqflags_t;
00162 
00163 static inline irqflags_t cpu_irq_save(void)
00164 {
00165         irqflags_t flags;
00166 
00167         flags = sysreg_read(AVR32_SR);
00168         cpu_irq_disable();
00169 
00170         return flags;
00171 }
00172 
00173 static inline void cpu_irq_restore(irqflags_t flags)
00174 {
00175         barrier();
00176         sysreg_write(AVR32_SR, flags);
00177 }
00178 
00179 static inline bool cpu_irq_is_enabled_flags(irqflags_t flags)
00180 {
00181         return !(flags & AVR32_SR_GM_MASK);
00182 }
00183 
00184 #define cpu_irq_is_enabled()    cpu_irq_is_enabled_flags(sysreg_read(AVR32_SR))
00185 
00187 
00188 
00197 static inline bool cpu_irq_level_is_enabled_flags(irqflags_t flags,
00198                 uint32_t level)
00199 {
00200         return !(flags & (1 << level));
00201 }
00202 
00212 #define cpu_irq_level_is_enabled(level)                                  \
00213         cpu_irq_level_is_enabled_flags(sysreg_read(AVR32_SR),             \
00214                         TPASTE3(AVR32_SR_I, level, M_OFFSET))
00215 
00216 #if defined(__GNUC__) || defined(__DOXYGEN__)
00217 
00224 #  define cpu_irq_enable_level(level)                                    \
00225         do {                                                             \
00226                 barrier();                                               \
00227                 __builtin_csrf(TPASTE3(AVR32_SR_I, level, M_OFFSET));    \
00228         } while (0)
00229 
00237 #  define cpu_irq_disable_level(level)                                   \
00238         do {                                                             \
00239                 __builtin_ssrf(TPASTE3(AVR32_SR_I, level, M_OFFSET));    \
00240                 barrier();                                               \
00241         } while (0)
00242 
00243 #elif (defined __ICCAVR32__)
00244 #  define cpu_irq_enable_level(level)                                          \
00245         do {                                                                   \
00246                 barrier();                                                     \
00247                 __clear_status_flag(TPASTE3(AVR32_SR_I, level, M_OFFSET));     \
00248         } while(0)
00249 #  define cpu_irq_disable_level(level)                                         \
00250         do {                                                                   \
00251                 __set_status_flag(TPASTE3(AVR32_SR_I, level, M_OFFSET));       \
00252                 barrier();                                                     \
00253         } while (0)
00254 #endif
00255 
00257 
00259 
00265 #define Enable_global_interrupt()            cpu_irq_enable()
00266 #define Disable_global_interrupt()           cpu_irq_disable()
00267 #define Is_global_interrupt_enabled()        cpu_irq_is_enabled()
00268 
00269 #define Enable_interrupt_level(level)        cpu_irq_enable_level(level)
00270 #define Disable_interrupt_level(level)       cpu_irq_disable_level(level)
00271 #define Is_interrupt_level_enabled(level)    cpu_irq_level_is_enabled(level)
00272 
00282 #define AVR32_ENTER_CRITICAL_REGION()                                          \
00283         {                                                                      \
00284                 Bool global_interrupt_enabled = Is_global_interrupt_enabled(); \
00285                 Disable_global_interrupt();
00286 
00293 #define AVR32_LEAVE_CRITICAL_REGION()                                          \
00294                 if (global_interrupt_enabled) Enable_global_interrupt();       \
00295         }
00296 
00298 
00300 
00301 #endif /* UTILS_INTERRUPT_INTERRUPT_H */
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