Xmega Application Note


DFLL Management
[Clock Management]

Collaboration diagram for DFLL Management:

Data Structures

struct  dfll_config
 Hardware-specific representation of DFLL configuration. More...

Interaction with the DFLL hardware



static int dfll_wait_for_accurate_lock (unsigned int dfll_id)
 Wait for the DFLL identified by dfll_id to achieve accurate lock.
static int dfll_wait_for_coarse_lock (unsigned int dfll_id)
 Wait for the DFLL identified by dfll_id to achieve coarse lock.
static int dfll_wait_for_fine_lock (unsigned int dfll_id)
 Wait for the DFLL identified by dfll_id to achieve fine lock.

Detailed Description

A Digital Frequency Locked Loop can be used to generate a highly accurate frequency from a slower-running reference clock, in much the same way as a PLL. DFLLs typically have shorter startup times and less jitter. They can also be used in open-loop mode to generate a less accurate frequency without the use of a reference clock.

There may be significant variations between platforms in the support for certain features.

Example: Setting up DFLL0 with default parameters and dithering enabled

The following example shows how to configure and enable DFLL0 in closed-loop mode using the default parameters specified through configuration symbols. It also enables dithering for better accuracy.

        struct dfll_config dfllcfg;

        dfll_config_defaults(&dfllcfg, 0);
        dfll_config_enable_dithering(&dfllcfg);
        dfll_enable(&dfllcfg, 0);
        dfll_wait_for_accurate_lock(0); 

When the last function call returns, DFLL0 is running at a frequency which matches the default configuration as accurately as possible. Any additional alterations to the default configuration can be added at the same place as the call to dfll_config_enable_dithering(), but note that the DFLL will never achieve "accurate" lock if dithering is disabled.


Function Documentation

static int dfll_wait_for_accurate_lock ( unsigned int  dfll_id  )  [inline, static]

Wait for the DFLL identified by dfll_id to achieve accurate lock.

Parameters:
dfll_id The ID of the DFLL to wait for.
Return values:
STATUS_OK The DFLL has achieved accurate lock.
ERR_TIMEOUT Timed out waiting for lock.

Definition at line 358 of file dfll.h.

00359 {
00360         /* TODO: Add timeout mechanism */
00361         while (!dfll_is_accurate_locked(dfll_id)) {
00362                 /* Do nothing */
00363         }
00364 
00365         return 0;
00366 }

static int dfll_wait_for_coarse_lock ( unsigned int  dfll_id  )  [inline, static]

Wait for the DFLL identified by dfll_id to achieve coarse lock.

Parameters:
dfll_id The ID of the DFLL to wait for.
Return values:
STATUS_OK The DFLL has achieved coarse lock.
ERR_TIMEOUT Timed out waiting for lock.

Definition at line 320 of file dfll.h.

00321 {
00322         /* TODO: Add timeout mechanism */
00323         while (!dfll_is_coarse_locked(dfll_id)) {
00324                 /* Do nothing */
00325         }
00326 
00327         return 0;
00328 }

static int dfll_wait_for_fine_lock ( unsigned int  dfll_id  )  [inline, static]

Wait for the DFLL identified by dfll_id to achieve fine lock.

Parameters:
dfll_id The ID of the DFLL to wait for.
Return values:
STATUS_OK The DFLL has achieved fine lock.
ERR_TIMEOUT Timed out waiting for lock.

Definition at line 339 of file dfll.h.

00340 {
00341         /* TODO: Add timeout mechanism */
00342         while (!dfll_is_fine_locked(dfll_id)) {
00343                 /* Do nothing */
00344         }
00345 
00346         return 0;
00347 }

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