Xmega Application Note


sysclk.h

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00001 
00038 #ifndef XMEGA_SYSCLK_H_INCLUDED
00039 #define XMEGA_SYSCLK_H_INCLUDED
00040 
00041 #include <board.h>
00042 #include <compiler.h>
00043 #include <parts.h>
00044 #include <ccp.h>
00045 #include <osc.h>
00046 #include <pll.h>
00047 
00048 // Include clock configuration for the project.
00049 #include <conf_clock.h>
00050 
00051 #ifdef __cplusplus
00052 extern "C" {
00053 #endif
00054 
00055 // Use 2 MHz with no prescaling if config was empty.
00056 #ifndef CONFIG_SYSCLK_SOURCE
00057 # define CONFIG_SYSCLK_SOURCE    SYSCLK_SRC_RC2MHZ
00058 #endif /* CONFIG_SYSCLK_SOURCE */
00059 
00060 #ifndef CONFIG_SYSCLK_PSADIV
00061 # define CONFIG_SYSCLK_PSADIV    SYSCLK_PSADIV_1
00062 #endif /* CONFIG_SYSCLK_PSADIV */
00063 
00064 #ifndef CONFIG_SYSCLK_PSBCDIV
00065 # define CONFIG_SYSCLK_PSBCDIV   SYSCLK_PSBCDIV_1_1
00066 #endif /* CONFIG_SYSCLK_PSBCDIV */
00067 
00084 
00085 
00086 
00087 #define SYSCLK_SRC_RC2MHZ    CLK_SCLKSEL_RC2M_gc
00088 
00089 #define SYSCLK_SRC_RC32MHZ   CLK_SCLKSEL_RC32M_gc
00090 
00091 #define SYSCLK_SRC_RC32KHZ   CLK_SCLKSEL_RC32K_gc
00092 
00093 #define SYSCLK_SRC_XOSC      CLK_SCLKSEL_XOSC_gc
00094 
00095 #define SYSCLK_SRC_PLL       CLK_SCLKSEL_PLL_gc
00096 
00097 
00099 
00100 #define SYSCLK_PSADIV_1      CLK_PSADIV_1_gc      //!< Do not prescale
00101 #define SYSCLK_PSADIV_2      CLK_PSADIV_2_gc      //!< Prescale CLKper4 by 2
00102 #define SYSCLK_PSADIV_4      CLK_PSADIV_4_gc      //!< Prescale CLKper4 by 4
00103 #define SYSCLK_PSADIV_8      CLK_PSADIV_8_gc      //!< Prescale CLKper4 by 8
00104 #define SYSCLK_PSADIV_16     CLK_PSADIV_16_gc     //!< Prescale CLKper4 by 16
00105 #define SYSCLK_PSADIV_32     CLK_PSADIV_32_gc     //!< Prescale CLKper4 by 32
00106 #define SYSCLK_PSADIV_64     CLK_PSADIV_64_gc     //!< Prescale CLKper4 by 64
00107 #define SYSCLK_PSADIV_128    CLK_PSADIV_128_gc    //!< Prescale CLKper4 by 128
00108 #define SYSCLK_PSADIV_256    CLK_PSADIV_256_gc    //!< Prescale CLKper4 by 256
00109 #define SYSCLK_PSADIV_512    CLK_PSADIV_512_gc    //!< Prescale CLKper4 by 512
00110 
00111 
00113 
00114 
00115 #define SYSCLK_PSBCDIV_1_1   CLK_PSBCDIV_1_1_gc
00116 
00117 #define SYSCLK_PSBCDIV_1_2   CLK_PSBCDIV_1_2_gc
00118 
00119 #define SYSCLK_PSBCDIV_4_1   CLK_PSBCDIV_4_1_gc
00120 
00121 #define SYSCLK_PSBCDIV_2_2   CLK_PSBCDIV_2_2_gc
00122 
00123 
00125 enum sysclk_port_id {
00126         SYSCLK_PORT_GEN,   
00127         SYSCLK_PORT_A,     
00128         SYSCLK_PORT_B,     
00129         SYSCLK_PORT_C,     
00130         SYSCLK_PORT_D,     
00131         SYSCLK_PORT_E,     
00132         SYSCLK_PORT_F,     
00133 };
00134 
00140 #define SYSCLK_DMA        PR_DMA_bm     //!< DMA Controller
00141 #define SYSCLK_EVSYS      PR_EVSYS_bm   //!< Event System
00142 #define SYSCLK_RTC        PR_RTC_bm     //!< Real-Time Counter
00143 #define SYSCLK_EBI        PR_EBI_bm     //!< Ext Bus Interface
00144 #define SYSCLK_AES        PR_AES_bm     //!< AES Module
00145 #define SYSCLK_USB        PR_USB_bm     //!< USB Module
00146 
00147 
00153 #define SYSCLK_AC         PR_AC_bm      //!< Analog Comparator
00154 #define SYSCLK_ADC        PR_ADC_bm     //!< A/D Converter
00155 #define SYSCLK_DAC        PR_DAC_bm     //!< D/A Converter
00156 
00157 
00163 #define SYSCLK_TC0        PR_TC0_bm      //!< Timer/Counter 0
00164 #define SYSCLK_TC1        PR_TC1_bm      //!< Timer/Counter 1
00165 #define SYSCLK_HIRES      PR_HIRES_bm    //!< Hi-Res Extension
00166 #define SYSCLK_SPI        PR_SPI_bm      //!< SPI controller
00167 #define SYSCLK_USART0     PR_USART0_bm   //!< USART 0
00168 #define SYSCLK_USART1     PR_USART1_bm   //!< USART 1
00169 #define SYSCLK_TWI        PR_TWI_bm      //!< TWI controller
00170 
00171 
00172 
00173 #if XMEGA_USB
00174 
00175 
00176 
00177 #define USBCLK_SRC_RCOSC    CLK_USBSRC_RC32M_gc
00178 
00179 #define USBCLK_SRC_PLL      CLK_USBSRC_PLL_gc
00180 
00181 
00193 #ifdef __DOXYGEN__
00194 # define CONFIG_USBCLK_SOURCE
00195 #endif
00196 
00197 #endif // XMEGA_USB
00198 
00199 #ifndef __ASSEMBLY__
00200 
00205 
00216 static inline uint32_t sysclk_get_main_hz(void)
00217 {
00218         switch (CONFIG_SYSCLK_SOURCE) {
00219         case SYSCLK_SRC_RC2MHZ:
00220                 return 2000000UL;
00221 
00222         case SYSCLK_SRC_RC32MHZ:
00223 #ifdef CONFIG_OSC_RC32_CAL
00224                 return CONFIG_OSC_RC32_CAL;
00225 #else
00226                 return 32000000UL;
00227 #endif
00228 
00229         case SYSCLK_SRC_RC32KHZ:
00230                 return 32768UL;
00231 
00232 #ifdef BOARD_XOSC_HZ
00233         case SYSCLK_SRC_XOSC:
00234                 return BOARD_XOSC_HZ;
00235 #endif
00236 
00237 #ifdef CONFIG_PLL0_SOURCE
00238         case SYSCLK_SRC_PLL:
00239                 return pll_get_default_rate(0);
00240 #endif
00241 
00242         default:
00243                 //unhandled_case(CONFIG_SYSCLK_SOURCE);
00244                 return 0;
00245         }
00246 }
00247 
00253 static inline uint32_t sysclk_get_per4_hz(void)
00254 {
00255         uint8_t shift = 0;
00256 
00257         if (CONFIG_SYSCLK_PSADIV & (1U << CLK_PSADIV_gp)) {
00258                 shift = (CONFIG_SYSCLK_PSADIV >> (1 + CLK_PSADIV_gp)) + 1;
00259         }
00260 
00261         return sysclk_get_main_hz() >> shift;
00262 }
00263 
00269 static inline uint32_t sysclk_get_per2_hz(void)
00270 {
00271         switch (CONFIG_SYSCLK_PSBCDIV) {
00272         case SYSCLK_PSBCDIV_1_1: /* Fall through */
00273         case SYSCLK_PSBCDIV_1_2:
00274                 return sysclk_get_per4_hz();
00275 
00276         case SYSCLK_PSBCDIV_4_1:
00277                 return sysclk_get_per4_hz() / 4;
00278 
00279         case SYSCLK_PSBCDIV_2_2:
00280                 return sysclk_get_per4_hz() / 2;
00281 
00282         default:
00283                 //unhandled_case(CONFIG_SYSCLK_PSBCDIV);
00284                 return 0;
00285         }
00286 }
00287 
00293 static inline uint32_t sysclk_get_per_hz(void)
00294 {
00295         if (CONFIG_SYSCLK_PSBCDIV & (1U << CLK_PSBCDIV_gp))
00296                 return sysclk_get_per2_hz() / 2;
00297         else
00298                 return sysclk_get_per2_hz();
00299 }
00300 
00304 static inline uint32_t sysclk_get_cpu_hz(void)
00305 {
00306         return sysclk_get_per_hz();
00307 }
00308 
00310 
00312 
00313 
00321 extern void sysclk_enable_module(enum sysclk_port_id port, uint8_t id);
00322 
00330 extern void sysclk_disable_module(enum sysclk_port_id port, uint8_t id);
00331 
00343 static inline bool sysclk_module_is_enabled(enum sysclk_port_id port,
00344                 uint8_t id)
00345 {
00346         uint8_t mask = *((uint8_t *)&PR.PRGEN + port);
00347         return (mask & id) == 0;
00348 }
00349 
00350 #if defined(CONFIG_USBCLK_SOURCE) || defined(__DOXYGEN__)
00351 extern void sysclk_enable_usb(uint8_t freq);
00352 extern void sysclk_disable_usb(void);
00353 #endif
00354 
00356 
00358 
00359 
00373 static inline void sysclk_set_prescalers(uint8_t psadiv, uint8_t psbcdiv)
00374 {
00375         ccp_write_io((uint8_t *)&CLK.PSCTRL, psadiv | psbcdiv);
00376 }
00377 
00384 static inline void sysclk_set_source(uint8_t src)
00385 {
00386         ccp_write_io((uint8_t *)&CLK.CTRL, src);
00387 }
00388 
00395 static inline void sysclk_lock(void)
00396 {
00397         ccp_write_io((uint8_t *)&CLK.LOCK, CLK_LOCK_bm);
00398 }
00399 
00401 
00403 
00404 
00405 extern void sysclk_init(void);
00406 
00408 
00409 #endif /* !__ASSEMBLY__ */
00410 
00412 
00413 #ifdef __cplusplus
00414 }
00415 #endif
00416 
00417 #endif /* XMEGA_SYSCLK_H_INCLUDED */
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