Xmega Application Note


reset_cause.h

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00001 
00038 #ifndef COMMON_DRIVERS_CPU_RESET_CAUSE_H
00039 #define COMMON_DRIVERS_CPU_RESET_CAUSE_H
00040 
00041 #include <parts.h>
00042 #include <stdbool.h>
00043 
00044 #if defined(XMEGA)
00045 # include "xmega_reset_cause.h"
00046 #elif defined(__AVR32__) || defined(__ICCAVR32__)
00047 # include "avr32_reset_cause.h"
00048 #else
00049 # error Unsupported chip type
00050 #endif
00051 
00070 /*
00071  * Sanity check of reset causes, define undefined reset causes to 0. Hence they
00072  * will always return false when querried.
00073  */
00074 #ifndef CHIP_RESET_CAUSE_BOD_CPU
00075 
00079 # define CHIP_RESET_CAUSE_BOD_CPU       0
00080 #endif
00081 #ifndef CHIP_RESET_CAUSE_BOD_IO
00082 
00086 # define CHIP_RESET_CAUSE_BOD_IO        0
00087 #endif
00088 #ifndef CHIP_RESET_CAUSE_CPU_ERROR
00089 
00090 # define CHIP_RESET_CAUSE_CPU_ERROR     0
00091 #endif
00092 #ifndef CHIP_RESET_CAUSE_EXTRST
00093 
00094 # define CHIP_RESET_CAUSE_EXTRST        0
00095 #endif
00096 #ifndef CHIP_RESET_CAUSE_JTAG
00097 
00098 # define CHIP_RESET_CAUSE_JTAG          0
00099 #endif
00100 #ifndef CHIP_RESET_CAUSE_OCD
00101 
00102 # define CHIP_RESET_CAUSE_OCD           0
00103 #endif
00104 #ifndef CHIP_RESET_CAUSE_POR
00105 
00106 # define CHIP_RESET_CAUSE_POR           0
00107 #endif
00108 #ifndef CHIP_RESET_CAUSE_SLEEP
00109 
00110 # define CHIP_RESET_CAUSE_SLEEP         0
00111 #endif
00112 #ifndef CHIP_RESET_CAUSE_SOFT
00113 
00114 # define CHIP_RESET_CAUSE_SOFT          0
00115 #endif
00116 #ifndef CHIP_RESET_CAUSE_SPIKE
00117 
00118 # define CHIP_RESET_CAUSE_SPIKE         0
00119 #endif
00120 #ifndef CHIP_RESET_CAUSE_WDT
00121 
00122 # define CHIP_RESET_CAUSE_WDT           0
00123 #endif
00124 
00128 enum reset_cause {
00130         RESET_CAUSE_BOD_CPU     = CHIP_RESET_CAUSE_BOD_CPU,
00132         RESET_CAUSE_BOD_IO      = CHIP_RESET_CAUSE_BOD_IO,
00134         RESET_CAUSE_CPU_ERROR   = CHIP_RESET_CAUSE_CPU_ERROR,
00136         RESET_CAUSE_EXTRST      = CHIP_RESET_CAUSE_EXTRST,
00138         RESET_CAUSE_JTAG        = CHIP_RESET_CAUSE_JTAG,
00140         RESET_CAUSE_OCD         = CHIP_RESET_CAUSE_OCD,
00142         RESET_CAUSE_POR         = CHIP_RESET_CAUSE_POR,
00144         RESET_CAUSE_SLEEP       = CHIP_RESET_CAUSE_SLEEP,
00146         RESET_CAUSE_SOFT        = CHIP_RESET_CAUSE_SOFT,
00148         RESET_CAUSE_SPIKE       = CHIP_RESET_CAUSE_SPIKE,
00150         RESET_CAUSE_WDT         = CHIP_RESET_CAUSE_WDT,
00151 };
00152 
00154 
00155 
00184 
00186 
00187 
00193 static inline bool reset_cause_is_cpu_brown_out_detected(void)
00194 {
00195         return (reset_cause_get_causes() & RESET_CAUSE_BOD_CPU);
00196 }
00197 
00203 static inline bool reset_cause_is_io_brown_out_detected(void)
00204 {
00205         return (reset_cause_get_causes() & RESET_CAUSE_BOD_IO);
00206 }
00207 
00214 static inline bool reset_cause_is_brown_out_detected(void)
00215 {
00216         return (reset_cause_is_cpu_brown_out_detected() ||
00217                         reset_cause_is_io_brown_out_detected());
00218 }
00219 
00225 static inline bool reset_cause_is_cpu_error(void)
00226 {
00227         return (reset_cause_get_causes() & RESET_CAUSE_CPU_ERROR);
00228 }
00229 
00235 static inline bool reset_cause_is_external_reset(void)
00236 {
00237         return (reset_cause_get_causes() & RESET_CAUSE_EXTRST);
00238 }
00239 
00245 static inline bool reset_cause_is_jtag(void)
00246 {
00247         return (reset_cause_get_causes() & RESET_CAUSE_JTAG);
00248 }
00249 
00255 static inline bool reset_cause_is_ocd(void)
00256 {
00257         return (reset_cause_get_causes() & RESET_CAUSE_OCD);
00258 }
00259 
00265 static inline bool reset_cause_is_power_on_reset(void)
00266 {
00267         return (reset_cause_get_causes() & RESET_CAUSE_POR);
00268 }
00269 
00275 static inline bool reset_cause_is_wake_from_shutdown_sleep(void)
00276 {
00277         return (reset_cause_get_causes() & RESET_CAUSE_SLEEP);
00278 }
00279 
00285 static inline bool reset_cause_is_software_reset(void)
00286 {
00287         return (reset_cause_get_causes() & RESET_CAUSE_SOFT);
00288 }
00289 
00295 static inline bool reset_cause_is_spike_detected(void)
00296 {
00297         return (reset_cause_get_causes() & RESET_CAUSE_SPIKE);
00298 }
00299 
00305 static inline bool reset_cause_is_watchdog(void)
00306 {
00307         return (reset_cause_get_causes() & RESET_CAUSE_WDT);
00308 }
00309 
00311 
00313 
00314 #endif /* COMMON_DRIVERS_CPU_RESET_CAUSE_H */
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Generated on Fri Oct 22 12:15:25 2010 for AVR1300 Using the Xmega ADC by doxygen 1.6.3