dfll.h
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00038 #ifndef CLK_DFLL_H_INCLUDED
00039 #define CLK_DFLL_H_INCLUDED
00040
00041 #include <parts.h>
00042 #include "conf_clock.h"
00043
00044 #if UC3L
00045 # include "uc3l/dfll.h"
00046 #else
00047 # error Unsupported chip type
00048 #endif
00049
00086
00087
00088
00101
00107
00108
00109
00235
00237
00238
00320 static inline int dfll_wait_for_coarse_lock(unsigned int dfll_id)
00321 {
00322
00323 while (!dfll_is_coarse_locked(dfll_id)) {
00324
00325 }
00326
00327 return 0;
00328 }
00329
00339 static inline int dfll_wait_for_fine_lock(unsigned int dfll_id)
00340 {
00341
00342 while (!dfll_is_fine_locked(dfll_id)) {
00343
00344 }
00345
00346 return 0;
00347 }
00348
00358 static inline int dfll_wait_for_accurate_lock(unsigned int dfll_id)
00359 {
00360
00361 while (!dfll_is_accurate_locked(dfll_id)) {
00362
00363 }
00364
00365 return 0;
00366 }
00367
00369
00370
00371 #endif