diff -uNr u-boot-1.2.0/board/silverbox/silverbox.c u-boot-1.2.0-pnx/board/silverbox/silverbox.c
--- u-boot-1.2.0/board/silverbox/silverbox.c	2011-05-13 18:12:05.009139001 +0200
+++ u-boot-1.2.0-pnx/board/silverbox/silverbox.c	2011-05-13 17:57:21.189139001 +0200
@@ -68,10 +68,13 @@
 
 int checkboard (void)
 {
-#if 0
-//#ifdef CONFIG_PCI
+
+#ifdef CONFIG_PCI
 	int mem_size = initdram(0) / (1024 * 1024);
 	int pci_mem_code;
+        
+        // clear global 2 register
+        writel(0, IP0128);
 
 	/* Calc the PCI mem size code */
 	if (mem_size >= 128)
@@ -84,45 +87,46 @@
 		pci_mem_code = IPA051_PCI_SETUP__BASExx_SIZ_16M;
 
 	/* Set PCI_XIO registers */
-	writel(PCIMEM_BASE, IPA051_PCI_BASE1_LO);
-	writel(PCIMEM_BASE + PCIMEM_SIZE + 1, IPA051_PCI_BASE1_HI);
-	writel(PCIIO_BASE, IPA051_PCI_BASE2_LO);
-	writel(PCIIO_BASE + PCIIO_SIZE + 1, IPA051_PCI_BASE2_HI);
+	writel(PCIMEM_BASE, IPA051 + IPA051_PCI_BASE1_LO);
+	writel(PCIMEM_BASE + PCIMEM_SIZE + 1, IPA051 + IPA051_PCI_BASE1_HI);
+	writel(PCIIO_BASE, IPA051 + IPA051_PCI_BASE2_LO);
+	writel(PCIIO_BASE + PCIIO_SIZE + 1, IPA051 + IPA051_PCI_BASE2_HI);
 
 	/* Send memory transaction via PCI_BASE2 */
-	writel(0x00000000, IPA051_PCI_IO);
+	writel(0x00000001, IPA051 + IPA051_PCI_IO);
 
 	/* Unlock the setup register */
-	writel(0xca, IPA051_UNLOCK_REGISTER);
-
+	writel(0xca, IPA051 + IPA051_UNLOCK_REGISTER);
+	
 	/*
 	 * BAR0 of IP A051 (pci base 10) must be zero in order for ide
 	 * to work, and in order for bus_to_baddr to work without any
 	 * hacks.
 	 */
-	writel(0x00000000, IPA051_BASE10);
+	writel(0x00000000, IPA051 + IPA051_BASE10);
 
 	/*
 	 * These two bars are set by default or the boot code.
 	 * However, it's safer to set them here so we're not boot
 	 * code dependent.
 	 */
-	writel(MMIO_BASE, IPA051_BASE14);		/* PNX MMIO */
-	writel(XIO_BASE, IPA051_BASE18);		/* XIO      */
+	writel(MMIO_BASE, IPA051 + IPA051_BASE14);		/* PNX MMIO */
+	writel(XIO_BASE, IPA051 + IPA051_BASE18);		/* XIO      */
 
 	writel( IPA051_PCI_SETUP__EN_TA |
 		IPA051_PCI_SETUP__EN_PCI2MMI |
 		IPA051_PCI_SETUP__EN_XIO |
-		IPA051_PCI_SETUP__BASE18_SIZ(IPA051_PCI_SETUP__BASExx_SIZ_128M) |
+		IPA051_PCI_SETUP__BASE18_SIZ(IPA051_PCI_SETUP__BASExx_SIZ_32M) |
 		IPA051_PCI_SETUP__EN_BASE18 |
 		IPA051_PCI_SETUP__EN_BASE14 |
 		IPA051_PCI_SETUP__BASE10_PREFETCHABLE |
 		IPA051_PCI_SETUP__BASE10_SIZ(pci_mem_code) |
 		IPA051_PCI_SETUP__EN_CONFIG_MANAG |
 		IPA051_PCI_SETUP__EN_PCI_ARB,		/* Enable PCI arbiter */
-		IPA051_PCI_SETUP );			/* PCI_SETUP */
+		IPA051 + IPA051_PCI_SETUP );			/* PCI_SETUP */
+
+	writel(0x00000000, IPA051 + IPA051_PCI_CONTROL);		/* PCI_CONTROL */
 
-	writel(0x00000000, IPA051_PCI_CONTROL);		/* PCI_CONTROL */
 #else
 	initdram(0);
 #endif /* CONFIG_PCI */
diff -uNr u-boot-1.2.0/drivers/natsemi.c u-boot-1.2.0-pnx/drivers/natsemi.c
--- u-boot-1.2.0/drivers/natsemi.c	2011-05-13 18:12:06.857139001 +0200
+++ u-boot-1.2.0-pnx/drivers/natsemi.c	2011-05-13 18:04:55.397139001 +0200
@@ -306,12 +306,11 @@
 			break;
 		}
 
-		pci_read_config_dword(devno, PCI_BASE_ADDRESS_0, &iobase);
+		pci_read_config_dword(devno, PCI_BASE_ADDRESS_1, &iobase);
 		iobase &= ~0x3;	/* bit 1: unused and bit 0: I/O Space Indicator */
-
+		
 		pci_write_config_dword(devno, PCI_COMMAND,
 				       PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
-
 		/* Check if I/O accesses and Bus Mastering are enabled. */
 		pci_read_config_dword(devno, PCI_COMMAND, &status);
 		if (!(status & PCI_COMMAND_MEMORY)) {
@@ -323,6 +322,11 @@
 		}
 
 		dev = (struct eth_device *) malloc(sizeof *dev);
+		if (!dev) {
+			printf("natsemi: Can not allocate memory\n");
+			break;
+		}
+		memset(dev, 0, sizeof(*dev));
 
 		sprintf(dev->name, "dp83815#%d", card_number);
 		dev->iobase = bus_to_phys(iobase);
diff -uNr u-boot-1.2.0/include/configs/silverbox.h u-boot-1.2.0-pnx/include/configs/silverbox.h
--- u-boot-1.2.0/include/configs/silverbox.h	2011-05-13 18:12:08.509139001 +0200
+++ u-boot-1.2.0-pnx/include/configs/silverbox.h	2011-05-12 19:51:37.041358001 +0200
@@ -40,9 +40,9 @@
 #define CONFIG_MIPS32					/* MIPS32 CPU core */
 #define CONFIG_MIPS_CPU_PR4450				/* Philips PR4450 implementation */
 
-#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
+#define CONFIG_BOOTDELAY	-1	/* autoboot after 5 seconds	*/
 
-#define CONFIG_BAUDRATE		38400
+#define CONFIG_BAUDRATE		115200
 
 /* valid baudrates */
 #define CFG_BAUDRATE_TABLE	{ 50, 75, 110, 134.5, 150, 300, 600, 1200, 2400, \
@@ -57,7 +57,8 @@
 		"panic=1\0"						\
 	""
 
-#define CONFIG_BOOTCOMMAND	""
+//#define CONFIG_BOOTCOMMAND	"cp.w 0x80200000 0x82000000 2020838;bootelf 0x82000000"
+#define CONFIG_BOOTCOMMAND ""
 
 #define CONFIG_COMMANDS	      (	(CONFIG_CMD_DFL		|\
 				 CFG_CMD_DHCP		|\
@@ -65,6 +66,7 @@
 				 CFG_CMD_ELF		|\
 				 CFG_CMD_I2C		|\
 				 CFG_CMD_EEPROM		|\
+                                 CFG_CMD_NET            |\
 				 CFG_CMD_PING)		&\
  				~(CFG_CMD_ENV | CFG_CMD_FLASH | CFG_CMD_IMLS ) )
 #include <cmd_confdefs.h>
@@ -128,12 +130,15 @@
 #define CONFIG_PCI
 #define CONFIG_PCI_PNP
 #define CONFIG_NXP_PCIXIO_IPA051
+#define CONFIG_PCI_SCAN_SHOW
 
 /*-----------------------------------------------------------------------
  * Network stuff
  */
-#define CONFIG_RTL8139
+#define CONFIG_NATSEMI
+#define NATSEMI_DEBUG
 #define CONFIG_NET_MULTI
+
 #define CONFIG_SERVERIP		192.168.1.10		/* IP address of tftp server */
 #define CONFIG_IPADDR		192.168.1.26		/* Our IP address */
 #define CONFIG_NETMASK		255.255.255.0		/* Our net mask */
diff -uNr u-boot-1.2.0/include/pnx8550_glb.h u-boot-1.2.0-pnx/include/pnx8550_glb.h
--- u-boot-1.2.0/include/pnx8550_glb.h	2011-05-13 17:50:46.401139001 +0200
+++ u-boot-1.2.0-pnx/include/pnx8550_glb.h	2011-05-13 18:13:10.889139001 +0200
@@ -37,9 +37,9 @@
 #define XIO_SIZE		0x04000000	/* 64MiB (pwr of 2, 1 MiB minimum) */
 #define MMIO_BASE		0x1BE00000
 #define MMIO_SIZE		0x00200000	/*  2MiB (pwr of 2, 1 MiB minimum) */
-#define PCIMEM_BASE		0x1C000000
+#define PCIMEM_BASE		0x12000000
 #define PCIMEM_SIZE		0x02000000	/* 32MiB (pwr of 2, 1 MiB minimum) */
-#define PCIIO_BASE		0x1E000000
+#define PCIIO_BASE		0x1c000000
 #define PCIIO_SIZE		0x02000000	/* 32MiB (pwr of 2, 1 MiB minimum) */
 
 /* MDCS/TDCS busses in MMIO */
diff -uNr u-boot-1.2.0/lib_mips/board.c u-boot-1.2.0-pnx/lib_mips/board.c
--- u-boot-1.2.0/lib_mips/board.c	2011-05-13 18:12:10.301139001 +0200
+++ u-boot-1.2.0-pnx/lib_mips/board.c	2011-05-13 14:23:30.093139002 +0200
@@ -194,7 +194,7 @@
 			hang ();
 		}
 	}
-	printf ("Debug: Init ready!\n");
+	debug ("Init ready!\n");
 
 	/*
 	 * Now that we have DRAM mapped and working, we can
diff -uNr u-boot-1.2.0/tools/gen_vmlinux_img.sh u-boot-1.2.0-pnx/tools/gen_vmlinux_img.sh
--- u-boot-1.2.0/tools/gen_vmlinux_img.sh	2011-05-13 18:12:10.849139001 +0200
+++ u-boot-1.2.0-pnx/tools/gen_vmlinux_img.sh	2011-05-09 15:48:55.253872001 +0200
@@ -12,6 +12,27 @@
 #   <be patient>
 #   bootelf 0x82000000
 
+# test if we should automate the boot procedure
+if [ $1 = "automate" ]; then
+
+  if [ ! -f vmlinux ]; then
+    echo "The elf kernel must be present in the u-boot directory before calling this script!"
+    exit 1
+  fi 
+
+  echo "entering size of kernel into the boot script"
+  cp include/configs/silverbox.tmplt include/configs/silverbox.h
+  ELFSIZE=$(ls -l vmlinux --block-size=4|cut -d' ' -f5)
+  sed -i "s/<ELFSIZE>/${ELFSIZE}/g" include/configs/silverbox.h
+
+  echo "creating u-boot"
+  make u-boot.bin
+
+fi
+
+echo "creating fake WinCe1.nb0"
 cp u-boot.bin WinCe1.nb0
 dd if=/dev/null of=WinCe1.nb0 bs=1 count=0 seek=1048576
 dd if=vmlinux of=WinCe1.nb0 oflag=append conv=notrunc
+
+echo "all ready for testing"