library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; library UNISIM; use UNISIM.VComponents.all; entity x_blockram is Port( DOA : out std_logic_vector(31 downto 0); -- Port A 32-bit Data Output DOB : out std_logic_vector(31 downto 0); -- Port B 32-bit Data Output DOPA : out std_logic_vector(3 downto 0); -- Port A 4-bit Parity Output DOPB : out std_logic_vector(3 downto 0); -- Port B 4-bit Parity Output ADDRA : in std_logic_vector(8 downto 0); -- Port A 9-bit Address Input ADDRB : in std_logic_vector(8 downto 0); -- Port B 9-bit Address Input CLKA : in std_logic; CLKB : in std_logic; -- Port B Clock DIA : in std_logic_vector(31 downto 0); -- Port A 32-bit Data Input DIB : in std_logic_vector(31 downto 0); -- Port B 32-bit Data Input DIPA : in std_logic_vector(3 downto 0); -- Port A 4-bit parity Input DIPB : in std_logic_vector(3 downto 0); -- Port-B 4-bit parity Input ENA : in std_logic; -- Port A RAM Enable Input ENB : in std_logic; -- PortB RAM Enable Input SSRA : in std_logic; -- Port A Synchronous Set/Reset Input SSRB : in std_logic; -- Port B Synchronous Set/Reset Input WEA : in std_logic; -- Port A Write Enable Input WEB : in std_logic); end x_blockram; architecture Behavioral of x_blockram is -- RAMB16_S36_S36: Virtex-II/II-Pro, Spartan-3/3E 512 x 32 + 4 Parity bits Dual-Port RAM -- Xilinx HDL Language Template version 7.1i component RAMB16_S36_S36 generic ( INIT_A : bit_vector := X"000000000"; -- Value of output RAM registers on Port A at startup INIT_B : bit_vector := X"000000000"; -- Value of output RAM registers on Port B at startup SRVAL_A : bit_vector := X"000000000"; -- Port A ouput value upon SSR assertion SRVAL_B : bit_vector := X"000000000"; -- Port B ouput value upon SSR assertion WRITE_MODE_A : string := "WRITE_FIRST"; -- WRITE_FIRST, READ_FIRST or NO_CHANGE WRITE_MODE_B : string := "WRITE_FIRST"; -- WRITE_FIRST, READ_FIRST or NO_CHANGE SIM_COLLISION_CHECK : string:= "ALL"; -- "NONE", "WARNING", "GENERATE_X_ONLY", "ALL" INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"); Port( DOA : out std_logic_vector(31 downto 0); -- Port A 32-bit Data Output DOB : out std_logic_vector(31 downto 0); -- Port B 32-bit Data Output DOPA : out std_logic_vector(3 downto 0); -- Port A 4-bit Parity Output DOPB : out std_logic_vector(3 downto 0); -- Port B 4-bit Parity Output ADDRA : in std_logic_vector(8 downto 0); -- Port A 9-bit Address Input ADDRB : in std_logic_vector(8 downto 0); -- Port B 9-bit Address Input CLKA : in std_logic; CLKB : in std_logic; -- Port B Clock DIA : in std_logic_vector(31 downto 0); -- Port A 32-bit Data Input DIB : in std_logic_vector(31 downto 0); -- Port B 32-bit Data Input DIPA : in std_logic_vector(3 downto 0); -- Port A 4-bit parity Input DIPB : in std_logic_vector(3 downto 0); -- Port-B 4-bit parity Input ENA : in std_logic; -- Port A RAM Enable Input ENB : in std_logic; -- PortB RAM Enable Input SSRA : in std_logic; -- Port A Synchronous Set/Reset Input SSRB : in std_logic; -- Port B Synchronous Set/Reset Input WEA : in std_logic; -- Port A Write Enable Input WEB : in std_logic); end component; begin x_blockram: RAMB16_S36_S36 port map ( DOA => DOA, -- Port A 32-bit Data Output DOB => DOB, -- Port B 32-bit Data Output DOPA => DOPA, -- Port A 4-bit Parity Output DOPB => DOPB, -- Port B 4-bit Parity Output ADDRA => ADDRA, -- Port A 9-bit Address Input ADDRB => ADDRB, -- Port B 9-bit Address Input CLKA => CLKA, -- Port A Clock CLKB => CLKB, -- Port B Clock DIA => DIA, -- Port A 32-bit Data Input DIB => DIB, -- Port B 32-bit Data Input DIPA => DIPA, -- Port A 4-bit parity Input DIPB => DIPB, -- Port-B 4-bit parity Input ENA => ENA, -- Port A RAM Enable Input ENB => ENB, -- PortB RAM Enable Input SSRA => SSRA, -- Port A Synchronous Set/Reset Input SSRB => SSRB, -- Port B Synchronous Set/Reset Input WEA => WEA, -- Port A Write Enable Input WEB => WEB -- Port B Write Enable Input ); end Behavioral;