library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; -- Uncomment the following lines to use the declarations that are -- provided for instantiating Xilinx primitive components. --library UNISIM; --use UNISIM.VComponents.all; entity gitarre is port(clock: in Std_Logic; reset: in Std_Logic; seg: out Std_Logic_Vector (6 downto 0); --7-Degment Anzeige point: out Std_Logic := '1'; --Punkt der 7-Sehment Anzeige enable: out Std_Logic_Vector (3 downto 0); --enable für die Anzeige tone_in: in Std_Logic); --Eingang für den Gitarrenton end gitarre; architecture Behavioral of gitarre is signal hzcounter: Integer Range 0 to 999 := 0; signal kilohzcounter: Integer Range 0 to 49999 := 0; signal kilohertz: Std_Logic := '0'; signal hertz: Std_Logic := '0'; signal freq: Std_Logic_Vector(15 downto 0) := "0000000000000000"; signal freq_puffer: Std_Logic_Vector(15 downto 0) := "0000000000000000"; signal dsp_puffer: Std_Logic_Vector(3 downto 0) := "0000"; signal cd: Std_Logic_Vector(1 downto 0) := "00"; begin point <= '1'; process(clock,tone_in,hertz,freq) begin if rising_edge(clock) then if reset = '1' then --freq <= "0000000000000000"; <-- hier wird die Fehlermeldung verursacht hzcounter <= 0; hertz <= '0'; else if hzcounter = 999 then hzcounter <= 0; hertz <= '1'; freq_puffer <= freq; --freq <= "0000000000000000"; <-- hier wird die Fehlermeldung verursacht else hertz <= '0'; end if; if kilohzcounter = 49999 then kilohzcounter <= 0; kilohertz <= '1'; hzcounter <= hzcounter +1; hertz <= '0'; else kilohzcounter <= kilohzcounter +1; kilohertz <= '0'; end if; end if; end if; if rising_edge(tone_in) then if freq(3 downto 0) = "1001" then if freq(7 downto 4) = "1001" then if freq(11 downto 8) = "1001" then if freq(15 downto 12) = "1001" then freq <= "0000000000000000" ; else freq <= (freq(15 downto 12) + 1) & "000000000000" ; end if ; else freq <= freq(15 downto 12) & (freq(11 downto 8) + 1) & "00000000" ; end if ; else freq <= freq(15 downto 8) & (freq(7 downto 4) + 1) & "0000" ; end if ; else freq <= freq(15 downto 4) & (freq(3 downto 0) + 1) ; end if ; end if ; end process; process(clock) begin if rising_edge(clock) then if kilohertz = '1' then cd(1 downto 0) <= cd(1 downto 0) + 1 ; end if ; case cd(1 downto 0) is when "00" => dsp_puffer <= freq_puffer(3 downto 0) ; enable <= "1110" ; when "01" => dsp_puffer <= freq_puffer(7 downto 4) ; enable <= "1101" ; when "10" => dsp_puffer <= freq_puffer(11 downto 8) ; enable <= "1011" ; when others => dsp_puffer <= freq_puffer(15 downto 12) ; enable <= "0111" ; end case ; case dsp_puffer is when "0000" => seg <= "0000001"; when "0001" => seg <= "1001111"; when "0010" => seg <= "0010010"; when "0011" => seg <= "0000110"; when "0100" => seg <= "1001100"; when "0101" => seg <= "0100100"; when "0110" => seg <= "0100000"; when "0111" => seg <= "0001111"; when "1000" => seg <= "0000000"; when others => seg <= "0000100"; end case; end if; end process; end Behavioral;