cpldfit: version H.41 Xilinx Inc. Fitter Report Design Name: sm_test Date: 8-23-2005, 8:14PM Device Used: XC9572-7-PC44 Fitting Status: Successful ************************* Mapped Resource Summary ************************** Macrocells Product Terms Function Block Registers Pins Used/Tot Used/Tot Inps Used/Tot Used/Tot Used/Tot 11 /72 ( 15%) 22 /360 ( 6%) 14 /144 ( 10%) 6 /72 ( 8%) 9 /34 ( 26%) ** Function Block Resources ** Function Mcells FB Inps Signals Pterms IO Block Used/Tot Used/Tot Used Used/Tot Used/Tot FB1 2/18 2/36 2 4/90 2/ 9 FB2 2/18 3/36 3 2/90 2/ 9 FB3 6/18 5/36 5 14/90 2/ 8 FB4 1/18 4/36 4 2/90 1/ 8 ----- ----- ----- ----- 11/72 14/144 22/360 7/34 * - Resource is exhausted ** Global Control Resources ** Signal 'clock' mapped onto global clock net GCK1. Global output enable net(s) unused. Signal 'reset' mapped onto global set/reset net GSR. ** Pin Resources ** Signal Type Required Mapped | Pin Type Used Total ------------------------------------|------------------------------------ Input : 3 3 | I/O : 10 28 Output : 7 7 | GCK/IO : 1 3 Bidirectional : 0 0 | GTS/IO : 0 2 GCK : 1 1 | GSR/IO : 1 1 GTS : 0 0 | GSR : 1 1 | ---- ---- Total 12 12 ** Power Data ** There are 11 macrocells in high performance mode (MCHP). There are 0 macrocells in low power mode (MCLP). End of Mapped Resource Summary ************************* Summary of Mapped Logic ************************ ** 7 Outputs ** Signal Total Total Loc Pin Pin Pin Pwr Slew Reg Init Name Pts Inps No. Type Use Mode Rate State LB 2 2 FB1_2 1 I/O O STD FAST RESET UB 2 2 FB1_8 4 I/O O STD FAST RESET CE 2 3 FB2_2 35 I/O O STD FAST RESET oe 0 0 FB2_8 38 I/O O STD FAST busy 2 4 FB3_2 11 I/O O STD FAST done 1 2 FB3_11 18 I/O O STD FAST WE 2 4 FB4_2 24 I/O O STD FAST RESET ** 4 Buried Nodes ** Signal Total Total Loc Pwr Reg Init Name Pts Inps Mode State UB_OBUF/UB_OBUF_SETF 2 5 FB3_15 STD CE_OBUF/CE_OBUF_RSTF 2 4 FB3_16 STD current_state_FFd2 3 4 FB3_17 STD RESET current_state_FFd1 4 5 FB3_18 STD RESET ** 5 Inputs ** Signal Loc Pin Pin Pin Name No. Type Use clock FB1_9 5~ GCK/I/O GCK highlow FB2_5 36 I/O I reset FB2_9 39~ GSR/I/O GSR write FB2_15 43 I/O I read FB4_11 28 I/O I Legend: Pin No. - ~ - User Assigned ************************** Function Block Details ************************ Legend: Total Pt - Total product terms used by the macrocell signal Imp Pt - Product terms imported from other macrocells Exp Pt - Product terms exported to other macrocells in direction shown Unused Pt - Unused local product terms remaining in macrocell Loc - Location where logic was mapped in device Pin Type/Use - I - Input GCK - Global Clock O - Output GTS - Global Output Enable (b) - Buried macrocell GSR - Global Set/Reset X(@) - Signal used as input (wire-AND input) to the macrocell logic. The number of Signals Used may exceed the number of FB Inputs Used due to wire-ANDing in the switch matrix. Pin No. - ~ - User Assigned *********************************** FB1 *********************************** Number of function block inputs used/remaining: 2/34 Number of signals used by logic mapping into function block: 2 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use (unused) 0 0 0 5 FB1_1 (b) LB 2 0 0 3 FB1_2 1 I/O O (unused) 0 0 0 5 FB1_3 (b) (unused) 0 0 0 5 FB1_4 (b) (unused) 0 0 0 5 FB1_5 2 I/O (unused) 0 0 0 5 FB1_6 3 I/O (unused) 0 0 0 5 FB1_7 (b) UB 2 0 0 3 FB1_8 4 I/O O (unused) 0 0 0 5 FB1_9 5 GCK/I/O GCK (unused) 0 0 0 5 FB1_10 (b) (unused) 0 0 0 5 FB1_11 6 GCK/I/O (unused) 0 0 0 5 FB1_12 (b) (unused) 0 0 0 5 FB1_13 (b) (unused) 0 0 0 5 FB1_14 7 GCK/I/O (unused) 0 0 0 5 FB1_15 8 I/O (unused) 0 0 0 5 FB1_16 (b) (unused) 0 0 0 5 FB1_17 9 I/O (unused) 0 0 0 5 FB1_18 (b) Signals Used by Logic in Function Block 1: CE_OBUF/CE_OBUF_RSTF 2: UB_OBUF/UB_OBUF_SETF Signal 1 2 3 4 Signals FB Name 0----+----0----+----0----+----0----+----0 Used Inputs LB XX...................................... 2 2 UB XX...................................... 2 2 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB2 *********************************** Number of function block inputs used/remaining: 3/33 Number of signals used by logic mapping into function block: 3 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use (unused) 0 0 0 5 FB2_1 (b) CE 2 0 0 3 FB2_2 35 I/O O (unused) 0 0 0 5 FB2_3 (b) (unused) 0 0 0 5 FB2_4 (b) (unused) 0 0 0 5 FB2_5 36 I/O I (unused) 0 0 0 5 FB2_6 37 I/O (unused) 0 0 0 5 FB2_7 (b) oe 0 0 0 5 FB2_8 38 I/O O (unused) 0 0 0 5 FB2_9 39 GSR/I/O GSR (unused) 0 0 0 5 FB2_10 (b) (unused) 0 0 0 5 FB2_11 40 GTS/I/O (unused) 0 0 0 5 FB2_12 (b) (unused) 0 0 0 5 FB2_13 (b) (unused) 0 0 0 5 FB2_14 42 GTS/I/O (unused) 0 0 0 5 FB2_15 43 I/O I (unused) 0 0 0 5 FB2_16 (b) (unused) 0 0 0 5 FB2_17 44 I/O (unused) 0 0 0 5 FB2_18 (b) Signals Used by Logic in Function Block 1: CE_OBUF/CE_OBUF_RSTF 2: current_state_FFd1 3: current_state_FFd2 Signal 1 2 3 4 Signals FB Name 0----+----0----+----0----+----0----+----0 Used Inputs CE XXX..................................... 3 3 oe ........................................ 0 0 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB3 *********************************** Number of function block inputs used/remaining: 5/31 Number of signals used by logic mapping into function block: 5 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use (unused) 0 0 0 5 FB3_1 (b) busy 2 0 0 3 FB3_2 11 I/O O (unused) 0 0 0 5 FB3_3 (b) (unused) 0 0 0 5 FB3_4 (b) (unused) 0 0 0 5 FB3_5 12 I/O (unused) 0 0 0 5 FB3_6 (b) (unused) 0 0 0 5 FB3_7 (b) (unused) 0 0 0 5 FB3_8 13 I/O (unused) 0 0 0 5 FB3_9 14 I/O (unused) 0 0 0 5 FB3_10 (b) done 1 0 0 4 FB3_11 18 I/O O (unused) 0 0 0 5 FB3_12 (b) (unused) 0 0 0 5 FB3_13 (b) (unused) 0 0 0 5 FB3_14 19 I/O UB_OBUF/UB_OBUF_SETF 2 0 0 3 FB3_15 20 I/O (b) CE_OBUF/CE_OBUF_RSTF 2 0 0 3 FB3_16 (b) (b) current_state_FFd2 3 0 0 2 FB3_17 22 I/O (b) current_state_FFd1 4 0 0 1 FB3_18 (b) (b) Signals Used by Logic in Function Block 1: current_state_FFd1.LFBK 3: highlow 5: write 2: current_state_FFd2.LFBK 4: read Signal 1 2 3 4 Signals FB Name 0----+----0----+----0----+----0----+----0 Used Inputs busy XX.XX................................... 4 4 done XX...................................... 2 2 UB_OBUF/UB_OBUF_SETF XXXXX................................... 5 5 CE_OBUF/CE_OBUF_RSTF XX.XX................................... 4 4 current_state_FFd2 XX.XX................................... 4 4 current_state_FFd1 XXXXX................................... 5 5 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB4 *********************************** Number of function block inputs used/remaining: 4/32 Number of signals used by logic mapping into function block: 4 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use (unused) 0 0 0 5 FB4_1 (b) WE 2 0 0 3 FB4_2 24 I/O O (unused) 0 0 0 5 FB4_3 (b) (unused) 0 0 0 5 FB4_4 (b) (unused) 0 0 0 5 FB4_5 25 I/O (unused) 0 0 0 5 FB4_6 (b) (unused) 0 0 0 5 FB4_7 (b) (unused) 0 0 0 5 FB4_8 26 I/O (unused) 0 0 0 5 FB4_9 27 I/O (unused) 0 0 0 5 FB4_10 (b) (unused) 0 0 0 5 FB4_11 28 I/O I (unused) 0 0 0 5 FB4_12 (b) (unused) 0 0 0 5 FB4_13 (b) (unused) 0 0 0 5 FB4_14 29 I/O (unused) 0 0 0 5 FB4_15 33 I/O (unused) 0 0 0 5 FB4_16 (b) (unused) 0 0 0 5 FB4_17 34 I/O (unused) 0 0 0 5 FB4_18 (b) Signals Used by Logic in Function Block 1: current_state_FFd1 3: read 4: write 2: current_state_FFd2 Signal 1 2 3 4 Signals FB Name 0----+----0----+----0----+----0----+----0 Used Inputs WE XXXX.................................... 4 4 0----+----1----+----2----+----3----+----4 0 0 0 0 ******************************* Equations ******************************** ********** Mapped Logic ********** FDCPE_CE: FDCPE port map (CE,'0','0',CE_OBUF/CE_OBUF_RSTF,CE_PRE); CE_PRE <= (NOT current_state_FFd1 AND NOT current_state_FFd2); CE_OBUF/CE_OBUF_RSTF <= ((write AND NOT read AND NOT current_state_FFd1.LFBK AND current_state_FFd2.LFBK) OR (NOT write AND read AND current_state_FFd1.LFBK AND NOT current_state_FFd2.LFBK)); FDCPE_LB: FDCPE port map (LB,'0','0',UB_OBUF/UB_OBUF_SETF,LB_PRE); LB_PRE <= (CE_OBUF/CE_OBUF_RSTF AND NOT UB_OBUF/UB_OBUF_SETF); FDCPE_UB: FDCPE port map (UB,'0','0',UB_CLR,UB_OBUF/UB_OBUF_SETF); UB_CLR <= (CE_OBUF/CE_OBUF_RSTF AND NOT UB_OBUF/UB_OBUF_SETF); UB_OBUF/UB_OBUF_SETF <= ((write AND highlow AND NOT current_state_FFd1.LFBK AND current_state_FFd2.LFBK) OR (NOT write AND read AND highlow AND current_state_FFd1.LFBK AND NOT current_state_FFd2.LFBK)); FDCPE_WE: FDCPE port map (WE,'0','0',WE_CLR,WE_PRE); WE_CLR <= (NOT current_state_FFd1 AND current_state_FFd2 AND write AND NOT read); WE_PRE <= (current_state_FFd1 AND NOT current_state_FFd2 AND NOT write AND read); busy <= ((write AND NOT read AND NOT current_state_FFd1.LFBK AND current_state_FFd2.LFBK) OR (NOT write AND read AND current_state_FFd1.LFBK AND NOT current_state_FFd2.LFBK)); FDCPE_current_state_FFd1: FDCPE port map (current_state_FFd1,current_state_FFd1_D,clock,reset,'0'); current_state_FFd1_D <= ((NOT write AND read) OR (current_state_FFd1.LFBK AND NOT current_state_FFd2.LFBK) OR (NOT write AND NOT current_state_FFd1.LFBK AND current_state_FFd2.LFBK) OR (NOT read AND NOT highlow AND NOT current_state_FFd1.LFBK AND current_state_FFd2.LFBK)); FDCPE_current_state_FFd2: FDCPE port map (current_state_FFd2,current_state_FFd2_D,clock,reset,'0'); current_state_FFd2_D <= ((read AND NOT current_state_FFd2.LFBK) OR (NOT write AND current_state_FFd1.LFBK AND current_state_FFd2.LFBK) OR (NOT write AND NOT current_state_FFd1.LFBK AND NOT current_state_FFd2.LFBK)); done <= (current_state_FFd1.LFBK AND current_state_FFd2.LFBK); oe <= '0'; Register Legend: FDCPE (Q,D,C,CLR,PRE); FTCPE (Q,D,C,CLR,PRE); LDCP (Q,D,G,CLR,PRE); ****************************** Device Pin Out ***************************** Device : XC9572-7-PC44 -------------------------------- /6 5 4 3 2 1 44 43 42 41 40 \ | 7 39 | | 8 38 | | 9 37 | | 10 36 | | 11 XC9572-7-PC44 35 | | 12 34 | | 13 33 | | 14 32 | | 15 31 | | 16 30 | | 17 29 | \ 18 19 20 21 22 23 24 25 26 27 28 / -------------------------------- Pin Signal Pin Signal No. Name No. Name 1 LB 23 GND 2 TIE 24 WE 3 TIE 25 TIE 4 UB 26 TIE 5 clock 27 TIE 6 TIE 28 read 7 TIE 29 TIE 8 TIE 30 TDO 9 TIE 31 GND 10 GND 32 VCC 11 busy 33 TIE 12 TIE 34 TIE 13 TIE 35 CE 14 TIE 36 highlow 15 TDI 37 TIE 16 TMS 38 oe 17 TCK 39 reset 18 done 40 TIE 19 TIE 41 VCC 20 TIE 42 TIE 21 VCC 43 write 22 TIE 44 TIE Legend : NC = Not Connected, unbonded pin PGND = Unused I/O configured as additional Ground pin TIE = Unused I/O floating -- must tie to VCC, GND or other signal VCC = Dedicated Power Pin GND = Dedicated Ground Pin TDI = Test Data In, JTAG pin TDO = Test Data Out, JTAG pin TCK = Test Clock, JTAG pin TMS = Test Mode Select, JTAG pin PROHIBITED = User reserved pin **************************** Compiler Options **************************** Following is a list of all global compiler options used by the fitter run. Device(s) Specified : xc9572-7-PC44 Optimization Method : SPEED Multi-Level Logic Optimization : ON Ignore Timing Specifications : OFF Default Register Power Up Value : LOW Keep User Location Constraints : ON What-You-See-Is-What-You-Get : OFF Exhaustive Fitting : OFF Keep Unused Inputs : OFF Slew Rate : FAST Power Mode : STD Ground on Unused IOs : OFF Global Clock Optimization : ON Global Set/Reset Optimization : ON Global Ouput Enable Optimization : ON FASTConnect/UIM optimzation : ON Local Feedback : ON Pin Feedback : ON Input Limit : 36 Pterm Limit : 25