| Design Name | sm_test | 
| Device, Speed (SpeedFile Version) | XC9572, -7 (3.0) | 
| Date Created | Tue Aug 23 20:14:45 2005 | 
| Created By | Timing Report Generator: version H.41 | 
| Copyright | Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved. | 
| Notes and Warnings | 
|---|
| Note: This design contains no timing constraints. | 
| Note: A default set of constraints using a delay of 0.000ns will be used for analysis. | 
| Performance Summary | |
|---|---|
| Min. Clock Period | 8.000 ns. | 
| Max. Clock Frequency (fSYSTEM) | 125.000 MHz. | 
| Limited by Clock Pulse Width for clock | |
| Clock to Setup (tCYC) | 8.000 ns. | 
| Pad to Pad Delay (tPD) | 7.500 ns. | 
| Setup to Clock at the Pad (tSU) | 4.500 ns. | 
| Clock Pad to Output Pad Delay (tCO) | 11.000 ns. | 
| Constraint Name | Requirement (ns) | Delay (ns) | Paths | Paths Failing | 
|---|---|---|---|---|
| TS1000 | 0.0 | 0.0 | 0 | 0 | 
| TS1001 | 0.0 | 0.0 | 0 | 0 | 
| TS1002 | 0.0 | 0.0 | 0 | 0 | 
| TS1003 | 0.0 | 0.0 | 0 | 0 | 
| TS1004 | 0.0 | 0.0 | 0 | 0 | 
| AUTO_TS_F2F | 0.0 | 8.0 | 4 | 4 | 
| AUTO_TS_P2P | 0.0 | 11.0 | 4 | 4 | 
| AUTO_TS_P2F | 0.0 | 6.0 | 6 | 6 | 
| AUTO_TS_F2P | 0.0 | 9.5 | 4 | 4 | 
| Path | Requirement (ns) | Delay (ns) | Slack (ns) | 
|---|
| Path | Requirement (ns) | Delay (ns) | Slack (ns) | 
|---|
| Path | Requirement (ns) | Delay (ns) | Slack (ns) | 
|---|
| Path | Requirement (ns) | Delay (ns) | Slack (ns) | 
|---|
| Path | Requirement (ns) | Delay (ns) | Slack (ns) | 
|---|
| Path | Requirement (ns) | Delay (ns) | Slack (ns) | 
|---|---|---|---|
| current_state_FFd1.Q to current_state_FFd1.D | 0.000 | 8.000 | -8.000 | 
| current_state_FFd1.Q to current_state_FFd2.D | 0.000 | 8.000 | -8.000 | 
| current_state_FFd2.Q to current_state_FFd1.D | 0.000 | 8.000 | -8.000 | 
| current_state_FFd2.Q to current_state_FFd2.D | 0.000 | 8.000 | -8.000 | 
| Path | Requirement (ns) | Delay (ns) | Slack (ns) | 
|---|---|---|---|
| clock to busy | 0.000 | 11.000 | -11.000 | 
| clock to done | 0.000 | 11.000 | -11.000 | 
| read to busy | 0.000 | 7.500 | -7.500 | 
| write to busy | 0.000 | 7.500 | -7.500 | 
| Path | Requirement (ns) | Delay (ns) | Slack (ns) | 
|---|---|---|---|
| highlow to current_state_FFd1.D | 0.000 | 6.000 | -6.000 | 
| read to current_state_FFd1.D | 0.000 | 6.000 | -6.000 | 
| read to current_state_FFd2.D | 0.000 | 6.000 | -6.000 | 
| Path | Requirement (ns) | Delay (ns) | Slack (ns) | 
|---|---|---|---|
| current_state_FFd1.Q to busy | 0.000 | 9.500 | -9.500 | 
| current_state_FFd1.Q to done | 0.000 | 9.500 | -9.500 | 
| current_state_FFd2.Q to busy | 0.000 | 9.500 | -9.500 | 
| current_state_FFd2.Q to done | 0.000 | 9.500 | -9.500 | 
| Clock | fEXT (MHz) | Reason | 
|---|---|---|
| clock | 125.000 | Limited by Clock Pulse Width for clock | 
| Source Pad | Setup to clk (edge) | Hold to clk (edge) | 
|---|---|---|
| highlow | 4.500 | 0.000 | 
| read | 4.500 | 0.000 | 
| write | 4.500 | 0.000 | 
| Destination Pad | Clock (edge) to Pad | 
|---|---|
| busy | 11.000 | 
| done | 11.000 | 
| Source | Destination | Delay | 
|---|---|---|
| current_state_FFd1.Q | current_state_FFd1.D | 8.000 | 
| current_state_FFd1.Q | current_state_FFd2.D | 8.000 | 
| current_state_FFd2.Q | current_state_FFd1.D | 8.000 | 
| current_state_FFd2.Q | current_state_FFd2.D | 8.000 | 
| Source Pad | Destination Pad | Delay | 
|---|---|---|
| read | busy | 7.500 | 
| write | busy | 7.500 |