Timing Report

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Design Name sm_test
Device, Speed (SpeedFile Version) XC9572, -7 (3.0)
Date Created Tue Aug 23 20:14:45 2005
Created By Timing Report Generator: version H.41
Copyright Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved.

Summary

Notes and Warnings
Note: This design contains no timing constraints.
Note: A default set of constraints using a delay of 0.000ns will be used for analysis.

Performance Summary
Min. Clock Period 8.000 ns.
Max. Clock Frequency (fSYSTEM) 125.000 MHz.
Limited by Clock Pulse Width for clock
Clock to Setup (tCYC) 8.000 ns.
Pad to Pad Delay (tPD) 7.500 ns.
Setup to Clock at the Pad (tSU) 4.500 ns.
Clock Pad to Output Pad Delay (tCO) 11.000 ns.

Timing Constraints

Constraint Name Requirement (ns) Delay (ns) Paths Paths Failing
TS1000 0.0 0.0 0 0
TS1001 0.0 0.0 0 0
TS1002 0.0 0.0 0 0
TS1003 0.0 0.0 0 0
TS1004 0.0 0.0 0 0
AUTO_TS_F2F 0.0 8.0 4 4
AUTO_TS_P2P 0.0 11.0 4 4
AUTO_TS_P2F 0.0 6.0 6 6
AUTO_TS_F2P 0.0 9.5 4 4


Constraint: TS1000

Description: PERIOD:PERIOD_WE_OBUF.CLKF:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1001

Description: PERIOD:PERIOD_UB_OBUF.CLKF:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1002

Description: PERIOD:PERIOD_LB_OBUF.CLKF:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1003

Description: PERIOD:PERIOD_CE_OBUF.CLKF:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1004

Description: PERIOD:PERIOD_clock:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: AUTO_TS_F2F

Description: MAXDELAY:FROM:FFS(*):TO:FFS(*):0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)
current_state_FFd1.Q to current_state_FFd1.D 0.000 8.000 -8.000
current_state_FFd1.Q to current_state_FFd2.D 0.000 8.000 -8.000
current_state_FFd2.Q to current_state_FFd1.D 0.000 8.000 -8.000
current_state_FFd2.Q to current_state_FFd2.D 0.000 8.000 -8.000


Constraint: AUTO_TS_P2P

Description: MAXDELAY:FROM:PADS(*):TO:PADS(*):0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)
clock to busy 0.000 11.000 -11.000
clock to done 0.000 11.000 -11.000
read to busy 0.000 7.500 -7.500
write to busy 0.000 7.500 -7.500


Constraint: AUTO_TS_P2F

Description: MAXDELAY:FROM:PADS(*):TO:FFS(*):0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)
highlow to current_state_FFd1.D 0.000 6.000 -6.000
read to current_state_FFd1.D 0.000 6.000 -6.000
read to current_state_FFd2.D 0.000 6.000 -6.000


Constraint: AUTO_TS_F2P

Description: MAXDELAY:FROM:FFS(*):TO:PADS(*):0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)
current_state_FFd1.Q to busy 0.000 9.500 -9.500
current_state_FFd1.Q to done 0.000 9.500 -9.500
current_state_FFd2.Q to busy 0.000 9.500 -9.500
current_state_FFd2.Q to done 0.000 9.500 -9.500



Number of constraints not met: 4

Data Sheet Report

Maximum External Clock Speeds

Clock fEXT (MHz) Reason
clock 125.000 Limited by Clock Pulse Width for clock

Setup/Hold Times for Clocks

Setup/Hold Times for Clock clock
Source Pad Setup to clk (edge) Hold to clk (edge)
highlow 4.500 0.000
read 4.500 0.000
write 4.500 0.000


Clock to Pad Timing

Clock clock to Pad
Destination Pad Clock (edge) to Pad
busy 11.000
done 11.000


Clock to Setup Times for Clocks

Clock to Setup for clock clock
Source Destination Delay
current_state_FFd1.Q current_state_FFd1.D 8.000
current_state_FFd1.Q current_state_FFd2.D 8.000
current_state_FFd2.Q current_state_FFd1.D 8.000
current_state_FFd2.Q current_state_FFd2.D 8.000


Pad to Pad List

Source Pad Destination Pad Delay
read busy 7.500
write busy 7.500



Number of paths analyzed: 18
Number of Timing errors: 18
Analysis Completed: Tue Aug 23 20:14:45 2005