Equations

********** Mapped Logic **********
FDCPE_CE: FDCPE port map (CE,'0','0',CE_OBUF/CE_OBUF_RSTF,CE_PRE);
     CE_PRE <= (NOT current_state_FFd1 AND NOT current_state_FFd2);
CE_OBUF/CE_OBUF_RSTF <= ((write AND NOT read AND NOT current_state_FFd1.LFBK AND
      current_state_FFd2.LFBK)
      OR (NOT write AND read AND current_state_FFd1.LFBK AND
      NOT current_state_FFd2.LFBK));
FDCPE_LB: FDCPE port map (LB,'0','0',UB_OBUF/UB_OBUF_SETF,LB_PRE);
     LB_PRE <= (CE_OBUF/CE_OBUF_RSTF AND NOT UB_OBUF/UB_OBUF_SETF);
FDCPE_UB: FDCPE port map (UB,'0','0',UB_CLR,UB_OBUF/UB_OBUF_SETF);
     UB_CLR <= (CE_OBUF/CE_OBUF_RSTF AND NOT UB_OBUF/UB_OBUF_SETF);
UB_OBUF/UB_OBUF_SETF <= ((write AND highlow AND NOT current_state_FFd1.LFBK AND
      current_state_FFd2.LFBK)
      OR (NOT write AND read AND highlow AND
      current_state_FFd1.LFBK AND NOT current_state_FFd2.LFBK));
FDCPE_WE: FDCPE port map (WE,'0','0',WE_CLR,WE_PRE);
     WE_CLR <= (NOT current_state_FFd1 AND current_state_FFd2 AND write AND
      NOT read);
     WE_PRE <= (current_state_FFd1 AND NOT current_state_FFd2 AND NOT write AND
      read);
busy <= ((write AND NOT read AND NOT current_state_FFd1.LFBK AND
      current_state_FFd2.LFBK)
      OR (NOT write AND read AND current_state_FFd1.LFBK AND
      NOT current_state_FFd2.LFBK));
FDCPE_current_state_FFd1: FDCPE port map (current_state_FFd1,current_state_FFd1_D,clock,reset,'0');
     current_state_FFd1_D <= ((NOT write AND read)
      OR (current_state_FFd1.LFBK AND NOT current_state_FFd2.LFBK)
      OR (NOT write AND NOT current_state_FFd1.LFBK AND
      current_state_FFd2.LFBK)
      OR (NOT read AND NOT highlow AND NOT current_state_FFd1.LFBK AND
      current_state_FFd2.LFBK));
FDCPE_current_state_FFd2: FDCPE port map (current_state_FFd2,current_state_FFd2_D,clock,reset,'0');
     current_state_FFd2_D <= ((read AND NOT current_state_FFd2.LFBK)
      OR (NOT write AND current_state_FFd1.LFBK AND
      current_state_FFd2.LFBK)
      OR (NOT write AND NOT current_state_FFd1.LFBK AND
      NOT current_state_FFd2.LFBK));
done <= (current_state_FFd1.LFBK AND current_state_FFd2.LFBK);
oe <= '0';
Register Legend:
      FDCPE (Q,D,C,CLR,PRE);
      FTCPE (Q,D,C,CLR,PRE);
      LDCP (Q,D,G,CLR,PRE);