void spi_fifo_init()										
{
// Initialize SPI FIFO registers
   SpiaRegs.SPICCR.bit.SPISWRESET=0; // Reset SCI

   SpiaRegs.SPICCR.all=0x000F;       //16-bit character, Loopback mode 
   SpiaRegs.SPICTL.all=0x001F;       //Interrupt enabled, Master/Slave XMIT enabled
   SpiaRegs.SPISTS.all=0x0000;
   SpiaRegs.SPIBRR=0x3;           // Baud rate
   SpiaRegs.SPIFFTX.all=0xC028;      // Enable FIFO's, set TX FIFO level to 8
   SpiaRegs.SPIFFRX.all=0x0028;      // Set RX FIFO level to 31
   SpiaRegs.SPIFFCT.all=0x00;
   SpiaRegs.SPIPRI.all=0x0010;
    
   SpiaRegs.SPICCR.bit.SPISWRESET=1;  // Enable SCI

   SpiaRegs.SPIFFTX.bit.TXFIFO=1;
   SpiaRegs.SPIFFRX.bit.RXFIFORESET=1; 
}

void spiTxFifo(void)
{
 	 
 	Uint16 Data;
 	Uint16 SPI;  
 	Uint16 ii;
 	External_Ram = 0x100000;
 	Data = *(unsigned volatile int*)External_Ram;
 	Data = Data >> 4;
 	SPI = 0 ;
 	SPI = SPI << 12;
 	SPI += Data;
    for(i=0;i<1;i++)
    {  
       SpiaRegs.SPITXBUF =SPI;      // Send data 
    }

    SpiaRegs.SPIFFTX.bit.TXFFINTCLR=1;  // Clear Interrupt flag
	PieCtrlRegs.PIEACK.all|=0x20;  		// Issue PIE ACK
}