.include "m8def.inc"
.def tmp = r16
.def tmp1 = r17
.equ ramstart = 0x60
.equ takt = 4000000 ;4MHz
.equ baud = 9600
.equ baudratenregister = (takt/(8*baud))-1



rjmp start
rjmp	interrupt0 ;=$001	; External Interrupt0 Vector Address
rjmp	INT1addr ;=$002	; External Interrupt1 Vector Address
rjmp	OC2addr  ;=$003	; Output Compare2 Interrupt Vector Address
rjmp	OVF2addr ;=$004	; Overflow2 Interrupt Vector Address
rjmp	ICP1addr ;=$005	; Input Capture1 Interrupt Vector Address
rjmp	OC1Aaddr ;=$006	; Output Compare1A Interrupt Vector Address
rjmp	OC1Baddr ;=$007	; Output Compare1B Interrupt Vector Address
rjmp	OVF1addr ;=$008	; Overflow1 Interrupt Vector Address
rjmp	timer0interrupt ;=$009	; Overflow0 Interrupt Vector Address
rjmp	SPIaddr  ;=$00a	; SPI Interrupt Vector Address
rjmp	URXCaddr ;=$00b	; USART Receive Complete Interrupt Vector Address
rjmp	UDREaddr ;=$00c	; USART Data Register Empty Interrupt Vector Address
rjmp	uartinterrupt ;=$00d	; USART Transmit Complete Interrupt Vector Address
rjmp	ADCCaddr ;=$00e	; ADC Interrupt Vector Address
rjmp	ERDYaddr ;=$00f	; EEPROM Interrupt Vector Address
rjmp	ACIaddr  ;=$010	; Analog Comparator Interrupt Vector Address
rjmp    TWIaddr  ;=$011   ; Irq. vector address for Two-Wire Interface
rjmp	SPMRaddr ;=$012	; SPM complete Interrupt Vector Address

start:
	ldi tmp, low(ramend)
	ldi tmp1, high(ramend)
	out spl,tmp
	out sph, tmp1
	ldi xl, low(ramstart)
	ldi xh, high(ramstart)
	clr tmp
	ldi tmp1,12
speicher_loeschen:
	st x+,tmp 
	dec tmp1
	brne speicher_loeschen
	out tcnt0,tmp1
	ldi tmp, 0<<cs02 | 0<<cs01 | 1<<cs00	;Vorteiler timer 0 = 8
	out tccr0,tmp
	ldi tmp,1<<toie0
	out timsk,tmp
	ldi tmp, 1<<isc01 | 0 <<isc00
	out mcucr,tmp
	ldi tmp, 1<<int0
	out gicr,tmp
	ldi tmp,low(baudratenregister)
	ldi tmp1,high(baudratenregister)
	out ubrrh,tmp1
	out ubrrl,tmp
	ldi tmp,0<<rxen | 1<<txen | 1<<rxb8 | 1<<txb8 | 0<<rxcie | 1<<txcie
	out ucsrb,tmp
	sei
d1:				;Hauptschleife
		sleep
		rjmp d1

interrupt0:
	push tmp
	push tmp1
	in tmp1,sreg
	push tmp1
	push xl
	push xh
	push yl
	push yh
	ldi xl,low(ramstart)
	ldi xh,high(ramstart)
	push xl
	push xh
	movw y,x
	adiw y,10
	ldi tmp,3
interrupt0_1:
	ld tmp1,x+
	push tmp1
	andi tmp1,0b00001111
	cpi tmp1,0xa
	brlt interrupt0_2
	subi tmp1,-7
interrupt0_2:
	subi tmp1,-0x30
	st -y,tmp1
	pop tmp1
	andi tmp1,0b11110000
	swap tmp1
	cpi tmp1,0xa
	brlt interrupt0_3
	subi tmp1, -7
interrupt0_3:
	subi tmp1,-0x30
	st -y,tmp1
	dec tmp
	brne interrupt0_1
	out udr,tmp1
	ldi tmp1,1
	sts ramstart+11,tmp1
	pop xh
	pop xl
	clr tmp1
	st x+,tmp1
	st x+,tmp1
	st x,tmp1
	pop yh
	pop yl
	pop xh
	pop xl
	pop tmp1
	out sreg,tmp1
	pop tmp1
	pop tmp
	reti

timer0interrupt:
	push tmp1
	in tmp1,sreg
	push tmp1
	push xl
	push xh
	lds xl,ramstart
	lds xh,ramstart+1
	adiw x,1
	brne timer0interrupt_1
	lds tmp1,ramstart+2
	inc tmp1
	sts ramstart+2,tmp1
timer0interrupt_1:
	sts ramstart+1,xh
	sts ramstart,xl
	pop xh
	pop xl
	pop tmp1
	out sreg,tmp1
	pop tmp1
	reti

uartinterrupt:
	push tmp1
	in tmp1,sreg
	push tmp1
	lds tmp1,ramstart+11
	cpi tmp1,8
	brlt uartinterrupt_1
	clr tmp1
	sts ramstart+11,tmp1
uartinterrupt_0:
	pop tmp1
	out sreg,tmp1
	pop tmp1
	reti
uartinterrupt_1:
	inc tmp1
	sts ramstart+11,tmp1
	cpi tmp1,8
	brlt uartinterrupt_2
	ldi tmp1, 13	;cr
	out udr,tmp1
	rjmp uartinterrupt_0
uartinterrupt_2:
	cpi tmp1,7
	brlt uartinterrupt_3
	ldi tmp1,10
	out udr,tmp1
	rjmp uartinterrupt_0
uartinterrupt_3:
	push xl
	push xh
	ldi xl,low(ramstart+3)
	ldi xh,high(ramstart+3)
	add xl,tmp1
	ld tmp1,x
	out udr,tmp1
	pop xh
	pop xl
	rjmp uartinterrupt_0