cpldfit:  version H.41                              Xilinx Inc.
                                  Fitter Report
Design Name: dffd                                Date: 10-23-2005,  1:11PM
Device Used: XC9536XL-5-VQ44
Fitting Status: Successful

*************************  Mapped Resource Summary  **************************

Macrocells     Product Terms    Function Block   Registers      Pins           
Used/Tot       Used/Tot         Inps Used/Tot    Used/Tot       Used/Tot       
2  /36  (  6%) 4   /180  (  2%) 6  /108 (  6%)   0  /36  (  0%) 2  /34  (  6%)

** Function Block Resources **

Function    Mcells      FB Inps     Pterms      IO          
Block       Used/Tot    Used/Tot    Used/Tot    Used/Tot    
FB1           1/18        3/54        2/90       1/17
FB2           1/18        3/54        2/90       1/17
             -----       -----       -----      -----    
              2/36        6/108       4/180      2/34 

* - Resource is exhausted

** Global Control Resources **

Global clock net(s) unused.
Global output enable net(s) unused.
Global set/reset net(s) unused.

** Pin Resources **

Signal Type    Required     Mapped  |  Pin Type            Used    Total 
------------------------------------|------------------------------------
Input         :    5           5    |  I/O              :     7      28
Output        :    2           2    |  GCK/IO           :     0       3
Bidirectional :    0           0    |  GTS/IO           :     0       2
GCK           :    0           0    |  GSR/IO           :     0       1
GTS           :    0           0    |
GSR           :    0           0    |
                 ----        ----
        Total      7           7

** Power Data **

There are 2 macrocells in high performance mode (MCHP).
There are 0 macrocells in low power mode (MCLP).
End of Mapped Resource Summary
*************************  Summary of Mapped Logic  ************************

** 2 Outputs **

Signal              Total Total Loc     Pin  Pin     Pin     Pwr  Slew Reg Init
Name                Pts   Inps          No.  Type    Use     Mode Rate State
X                   2     3     FB1_2   41   I/O     O       STD  FAST 
Y                   2     3     FB2_2   38   I/O     O       STD  FAST 

** 5 Inputs **

Signal              Loc     Pin  Pin     Pin     
Name                        No.  Type    Use     
X0                  FB2_8   31   I/O     I
ENABLE              FB2_9   30   I/O     I
X1                  FB2_11  28   I/O     I
Y0                  FB2_13  23   I/O     I
Y1                  FB2_15  21   I/O     I

Legend:
Pin No. - ~ - User Assigned
**************************  Function Block Details  ************************
Legend:
Total Pt     - Total product terms used by the macrocell signal
Imp Pt       - Product terms imported from other macrocells
Exp Pt       - Product terms exported to other macrocells
               in direction shown
Unused Pt    - Unused local product terms remaining in macrocell
Loc          - Location where logic was mapped in device
Pin Type/Use - I  - Input             GCK - Global Clock
               O  - Output            GTS - Global Output Enable
              (b) - Buried macrocell  GSR - Global Set/Reset
X            - Signal used as input to the macrocell logic.
Pin No.      - ~  - User Assigned
*********************************** FB1  ***********************************
Number of function block inputs used/remaining:               3/51
Number of signals used by logic mapping into function block:  3
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
(unused)              0       0     0   5     FB1_1   40    I/O     
X                     2       0     0   3     FB1_2   41    I/O     O
(unused)              0       0     0   5     FB1_3   43    GCK/I/O 
(unused)              0       0     0   5     FB1_4   42    I/O     
(unused)              0       0     0   5     FB1_5   44    GCK/I/O 
(unused)              0       0     0   5     FB1_6   2     I/O     
(unused)              0       0     0   5     FB1_7   1     GCK/I/O 
(unused)              0       0     0   5     FB1_8   3     I/O     
(unused)              0       0     0   5     FB1_9   5     I/O     
(unused)              0       0     0   5     FB1_10  6     I/O     
(unused)              0       0     0   5     FB1_11  7     I/O     
(unused)              0       0     0   5     FB1_12  8     I/O     
(unused)              0       0     0   5     FB1_13  12    I/O     
(unused)              0       0     0   5     FB1_14  13    I/O     
(unused)              0       0     0   5     FB1_15  14    I/O     
(unused)              0       0     0   5     FB1_16  16    I/O     
(unused)              0       0     0   5     FB1_17  18    I/O     
(unused)              0       0     0   5     FB1_18        (b)     

Signals Used by Logic in Function Block
  1: ENABLE             2: X0                 3: X1 

Signal                        1         2         3         4 FB
Name                0----+----0----+----0----+----0----+----0 Inputs
X                    XXX..................................... 3
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*********************************** FB2  ***********************************
Number of function block inputs used/remaining:               3/51
Number of signals used by logic mapping into function block:  3
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
(unused)              0       0     0   5     FB2_1   39    I/O     
Y                     2       0     0   3     FB2_2   38    I/O     O
(unused)              0       0     0   5     FB2_3   36    GTS/I/O 
(unused)              0       0     0   5     FB2_4   37    I/O     
(unused)              0       0     0   5     FB2_5   34    GTS/I/O 
(unused)              0       0     0   5     FB2_6   33    GSR/I/O 
(unused)              0       0     0   5     FB2_7   32    I/O     
(unused)              0       0     0   5     FB2_8   31    I/O     I
(unused)              0       0     0   5     FB2_9   30    I/O     I
(unused)              0       0     0   5     FB2_10  29    I/O     
(unused)              0       0     0   5     FB2_11  28    I/O     I
(unused)              0       0     0   5     FB2_12  27    I/O     
(unused)              0       0     0   5     FB2_13  23    I/O     I
(unused)              0       0     0   5     FB2_14  22    I/O     
(unused)              0       0     0   5     FB2_15  21    I/O     I
(unused)              0       0     0   5     FB2_16  20    I/O     
(unused)              0       0     0   5     FB2_17  19    I/O     
(unused)              0       0     0   5     FB2_18        (b)     

Signals Used by Logic in Function Block
  1: ENABLE             2: Y0                 3: Y1 

Signal                        1         2         3         4 FB
Name                0----+----0----+----0----+----0----+----0 Inputs
Y                    XXX..................................... 3
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*******************************  Equations  ********************************

********** Mapped Logic **********


X <= ((X1 AND ENABLE)
	OR (NOT ENABLE AND X0));


Y <= ((ENABLE AND Y1)
	OR (NOT ENABLE AND Y0));

Register Legend:
 FDCPE (Q,D,C,CLR,PRE,CE); 
 FTCPE (Q,D,C,CLR,PRE,CE); 
 LDCP  (Q,D,G,CLR,PRE); 

******************************  Device Pin Out *****************************

Device : XC9536XL-5-VQ44


   --------------------------------  
  /44 43 42 41 40 39 38 37 36 35 34 \
 | 1                             33 | 
 | 2                             32 | 
 | 3                             31 | 
 | 4                             30 | 
 | 5         XC9536XL-5-VQ44     29 | 
 | 6                             28 | 
 | 7                             27 | 
 | 8                             26 | 
 | 9                             25 | 
 | 10                            24 | 
 | 11                            23 | 
 \ 12 13 14 15 16 17 18 19 20 21 22 /
   --------------------------------  


Pin Signal                         Pin Signal                        
No. Name                           No. Name                          
  1 KPR                              23 Y0                            
  2 KPR                              24 TDO                           
  3 KPR                              25 GND                           
  4 GND                              26 VCC                           
  5 KPR                              27 KPR                           
  6 KPR                              28 X1                            
  7 KPR                              29 KPR                           
  8 KPR                              30 ENABLE                        
  9 TDI                              31 X0                            
 10 TMS                              32 KPR                           
 11 TCK                              33 KPR                           
 12 KPR                              34 KPR                           
 13 KPR                              35 VCC                           
 14 KPR                              36 KPR                           
 15 VCC                              37 KPR                           
 16 KPR                              38 Y                             
 17 GND                              39 KPR                           
 18 KPR                              40 KPR                           
 19 KPR                              41 X                             
 20 KPR                              42 KPR                           
 21 Y1                               43 KPR                           
 22 KPR                              44 KPR                           


Legend :  NC  = Not Connected, unbonded pin
         PGND = Unused I/O configured as additional Ground pin
         TIE  = Unused I/O floating -- must tie to VCC, GND or other signal
         KPR  = Unused I/O with weak keeper (leave unconnected)
         VCC  = Dedicated Power Pin
         GND  = Dedicated Ground Pin
         TDI  = Test Data In, JTAG pin
         TDO  = Test Data Out, JTAG pin
         TCK  = Test Clock, JTAG pin
         TMS  = Test Mode Select, JTAG pin
  PROHIBITED  = User reserved pin
****************************  Compiler Options  ****************************

Following is a list of all global compiler options used by the fitter run.

Device(s) Specified                         : xc9536xl-5-VQ44
Optimization Method                         : SPEED
Multi-Level Logic Optimization              : ON
Ignore Timing Specifications                : OFF
Default Register Power Up Value             : LOW
Keep User Location Constraints              : ON
What-You-See-Is-What-You-Get                : OFF
Exhaustive Fitting                          : OFF
Keep Unused Inputs                          : OFF
Slew Rate                                   : FAST
Power Mode                                  : STD
Ground on Unused IOs                        : OFF
Set I/O Pin Termination                     : KEEPER
Global Clock Optimization                   : ON
Global Set/Reset Optimization               : ON
Global Ouput Enable Optimization            : ON
Input Limit                                 : 54
Pterm Limit                                 : 25