-- WARNING: Do NOT edit the input and output ports in this file in a text -- editor if you plan to continue editing the block that represents it in -- the Block Editor! File corruption is VERY likely to occur. -- Copyright (C) 1991-2005 Altera Corporation -- Any megafunction design, and related netlist (encrypted or decrypted), -- support information, device programming or simulation file, and any other -- associated documentation or information provided by Altera or a partner -- under Altera's Megafunction Partnership Program may be used only -- to program PLD devices (but not masked PLD devices) from Altera. Any -- other use of such megafunction design, netlist, support information, -- device programming or simulation file, or any other related documentation -- or information is prohibited for any other purpose, including, but not -- limited to modification, reverse engineering, de-compiling, or use with -- any other silicon devices, unless such use is explicitly licensed under -- a separate agreement with Altera or a megafunction partner. Title to the -- intellectual property, including patents, copyrights, trademarks, trade -- secrets, or maskworks, embodied in any such megafunction design, netlist, -- support information, device programming or simulation file, or any other -- related documentation or information provided by Altera or a megafunction -- partner, remains with Altera, the megafunction partner, or their respective -- licensors. No other licenses, including any licenses needed under any third -- party's intellectual property, are provided herein. -- Generated by Quartus II Version 4.2 (Build Build 178 01/19/2005) -- Created on Tue Nov 01 17:42:27 2005 LIBRARY ieee; USE ieee.std_logic_1164.all; -- Entity Declaration ENTITY ADWLTC1286 IS -- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE! PORT ( clk : IN STD_LOGIC; Data : IN STD_LOGIC; CS : OUT STD_LOGIC; DataLTC : OUT STD_LOGIC_VECTOR(11 downto 0) ); -- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE! END ADWLTC1286; -- Architecture Body ARCHITECTURE ADWLTC1286_architecture OF ADWLTC1286 IS BEGIN process (clk, Data) variable TMP: STD_LOGIC_VECTOR (11 downto 0); variable ct: Integer :=0; constant LOW : STD_LOGIC:='0'; constant HIGH :STD_LOGIC:='1'; begin if clk = '0' and clk'event then case ct IS when 0 => CS <= HIGH; ct:= ct+1; when 1 => CS <= LOW; ct:= ct+1; when 3 to 4 => ct:= ct+1; when 5 => TMP(11) := Data; ct:= ct+1; when 6 => TMP(10) := Data; ct:= ct+1; when 7 => TMP(9) := Data; ct:= ct+1; when 8 => TMP(8) := Data; ct:= ct+1; when 9 => TMP(7) := Data; ct:= ct+1; when 10 => TMP(6) := Data; ct:= ct+1; when 11 => TMP(5) := Data; ct:= ct+1; when 12 => TMP(4) := Data; ct:= ct+1; when 13 => TMP(3) := Data; ct:= ct+1; when 14 => TMP(2) := Data; ct:= ct+1; when 15 => TMP(1) := Data; ct:= ct+1; when 16 => TMP(0) := Data; ct:= ct+1; when 17 => CS <= HIGH; ct:= ct+1; DataLTC <= TMP; --DataLTC <= ("111010000000"); when others => CS <= HIGH; ct:=0; end case; end if; DataLTC <= TMP; end process; END ADWLTC1286_architecture;