-------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 10:38:02 12/19/05 -- Design Name: -- Module Name: Clock1_to_Clock2_adaption - Behavioral -- Project Name: -- Target Device: -- Tool versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- -------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. library UNISIM; use UNISIM.VComponents.all; entity Clock1_to_Clock2_adaption is Generic( CLOCK_DIVIDE : real := 2.0 ); Port ( Clock1_in : in std_logic; -- clk : in std_logic; -- rst : in std_logic; Clock2_out : out std_logic ); end Clock1_to_Clock2_adaption; architecture Behavioral of Clock1_to_Clock2_adaption is attribute BOX_TYPE: string; component CLKDLL generic( CLKDV_DIVIDE: real := 2.0; DUTY_CYCLE_CORRECTION: boolean := TRUE); port( CLKFB: in std_logic; CLKIN: in std_logic; RST: in std_logic; CLK0: out std_logic; CLK180: out std_logic; CLK270: out std_logic; CLK2X: out std_logic; CLK90: out std_logic; CLKDV: out std_logic; LOCKED: out std_logic); end component; attribute BOX_TYPE of CLKDLL: component is "BLACK_BOX"; component BUFG port( I: in std_logic; O: out std_logic); end component; attribute BOX_TYPE of BUFG: component is "BLACK_BOX"; component IBUFG port( I: in std_logic; O: out std_logic); end component; attribute BOX_TYPE of IBUFG: component is "BLACK_BOX"; component OBUF port( I: in std_logic; O: out std_logic); end component; attribute BOX_TYPE of OBUF: component is "BLACK_BOX"; Signal Clk1 : std_logic := '0' ; Signal Clk1d : std_logic := '0'; Signal Clk0_Buf : std_logic := '0'; Signal Clk1_Buf : std_logic := '0'; Signal Clk1d_Buf : std_logic := '0'; Signal DLL1_Locked : std_logic := '0'; Signal DLL1_Locked_Buf : std_logic := '0'; begin DLL1: CLKDLL generic map( CLKDV_DIVIDE => CLOCK_DIVIDE) port map( CLKFB=>Clk1_Buf, CLKIN=>Clk0_Buf, RST=>'0', CLKDV=>Clk1d, CLK0=>Clk1, CLK2X=>open, CLK90=>open, CLK180=>open, CLK270=>open, LOCKED=>DLL1_Locked); I1: IBUFG port map(I => Clock1_in, O => Clk0_Buf); B1: BUFG port map(I => Clk1, O => Clk1_Buf); B2: BUFG port map(I => Clk1d, O => Clk1d_Buf); O1: OBUF port map (I => DLL1_Locked, O => DLL1_Locked_Buf); Clock2_out <= Clk1d_Buf when DLL1_Locked_Buf = '1' else '0'; end Behavioral;