-- generation.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library APA;

entity takt is 

    port (clock, busyadc: in std_logic;
	      clockad, switch, convst, rd, cs: out std_logic); 	
    Signal count: integer range 0 to 34;
    Signal count1: integer range 0 to 1333;        					    
	
end takt;


architecture behavior of takt is

begin

takt: process (clock,busyadc) is

begin

if rising_edge(clock) then
    count1 <= count1+1;
            if count1>=0 and count1<=666 then
    		    clockad<='0';
    	    elsif count1>=666 and count1<1333 then
    		    clockad<='1';
    	    elsif count1>=1333 then
                count1<=0;
            end if;
end if;

-------------------------------------------------------------------------------------------------

if rising_edge(clockad) then
    count <= count+1;    
        	                        
            if count>=0 and count<17 then
             switch<='0';
             convst<='0';
             rd<='1';
             cs<='1';             
            elsif count=17 and busyadc<='0' then
             switch<='0';
             convst<='1';
             rd<='0';
             cs<='0';
            elsif count>17 and count<34 then
             switch<='1';
             convst<='0';
             rd<='1';
             cs<='1';
            elsif count>=34 and busyadc<='0' then
             switch<='1';
             convst<='1';
             rd<='0';
             cs<='0';
             count<=0;
        	end if;
end if;

end process;

end behavior;