-- generation.vhd LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_unsigned.ALL; LIBRARY APA; ENTITY takt IS PORT (clock, busyadc : IN STD_LOGIC; clockad, switch, convst, rd, cs : OUT STD_LOGIC); SIGNAL count : INTEGER RANGE 0 TO 34; SIGNAL count1 : INTEGER RANGE 0 TO 1333; SIGNAL busyadc_sync : STD_LOGIC_VECTOR(3 DOWNTO 0); END takt; ARCHITECTURE behavior OF takt IS BEGIN takt : PROCESS (clock) IS BEGIN IF rising_edge(clock) THEN --default for pulsed sigs clockad <= '0'; --synchronieser fpr busyadc busyadc_sync(0) <= busyadc; busyadc_sync(3 DOWNTO 1) <= busyadc_sync(2 DOWNTO 0); --counting clocks IF count1 = 1333 THEN count1 <= 0; ELSE count1 <= count1+1; END IF; --clockdivider, generating pulse IF count1 = 667 THEN clockad <= '1'; END IF; --counter 0 => 34 IF clockad = '1' THEN IF count = 34 THEN count <= 0; ELSE count <= count+1; END IF; END IF; --ausgangcoder IF count = 0 THEN switch <= '0'; convst <= '0'; rd <= '1'; cs <= '1'; ELSIF count = 17 AND busyadc_sync(3 DOWNTO 2) = "00" THEN switch <= '0'; convst <= '1'; rd <= '0'; cs <= '0'; ELSIF count = 18 THEN switch <= '1'; convst <= '0'; rd <= '1'; cs <= '1'; ELSIF count = 34 AND busyadc_sync(3 DOWNTO 2) = "00" THEN switch <= '1'; convst <= '1'; rd <= '0'; cs <= '0'; END IF; END IF; END PROCESS; END behavior;