void Hardware::ADC_ReadData(unsigned int channel, unsigned char *signal, unsigned int int_count, bool invert)
{
	channel--;										// convert real channel number to logical channel 

	volatile unsigned long* regAddr = (unsigned long *) RegADC[channel];
	unsigned long *uint32_buffer;
	unsigned int read_out_cnt = int_count + 1;						// because of below pre-decrement
	unsigned int *adc_offs = (unsigned int *) _ADC_Offset[channel];				// assign 32 bit integer pointer to offset bytes

	// delay compensation in fast acquisition TB (1 GSa/S) 
	if(MainTimebase < 8)
	{	
		signal += _ChannelDelay[channel];						// shift buffer address (1 byte = 1nS)
	}

	uint32_buffer = (unsigned long *) signal;						// point with 32 bit integer to the signal buffer


	// The Signal comes head over heals -> so we have to invert it for correct
	// display. Therefor we only have to adjust the virtual zero in inverted mode.
	if (invert)
	{
		unsigned char adc_v_zero = _ADC_VirtualZero[channel] << 1;
		unsigned long adc_v_zero32 = 0;

		// shift 8 bit virtual ADC-zero byte for byte into 32 bit integer
		adc_v_zero32 = (int)adc_v_zero;
		adc_v_zero32 = adc_v_zero32 << 8;
		adc_v_zero32 = adc_v_zero32 | (int)adc_v_zero;
		adc_v_zero32 = adc_v_zero32 << 8;
		adc_v_zero32 = adc_v_zero32 | (int)adc_v_zero;
		adc_v_zero32 = adc_v_zero32 << 8;
		adc_v_zero32 = adc_v_zero32 | (int)adc_v_zero;


		if (MainTimebase < 11 || USTB_Mode != USTB_OFF)					// Highspeed  -> 16KB memory and all 4 ADC
		{ 
			// read byte data integer aligned from FPGA register
			while (--read_out_cnt)
			{
				*uint32_buffer++ = adc_v_zero32 + (*regAddr + *adc_offs);	// make offset correction for all 4 bytes in one step
			}									// and copy bytes integer aligned into the signal buffer
		}
		else										// Lowspeed -> 4kB memory and only one ADC
		{
			// read byte data integer aligned from FPGA register
			while (--read_out_cnt)
			{
				*signal++ = adc_v_zero + (unsigned char)(*regAddr + *adc_offs);	// make offset correction for all 4 bytes in one step
			}									// and copy the first byte into the signal buffer
		}
	}
	else
	{
		if (MainTimebase < 11 || USTB_Mode != USTB_OFF)					// Highspeed  -> 16KB memory and all 4 ADC
		{ 
			// read byte data integer aligned from FPGA register
			while (--read_out_cnt)
			{
				*uint32_buffer++ = ~(*regAddr + *adc_offs ) + 0x02020202;	// make offset correction for all 4 bytes in one step
			}									// and copy bytes integer aligned into the signal buffer
		}
		else										// Lowspeed -> 4kB memory and only one ADC
		{
			// read byte data integer aligned from FPGA register
			while (--read_out_cnt)
			{
				*signal++ = ~(unsigned char)(*regAddr + *adc_offs) + 2;		// make offset correction for all 4 bytes in one step
			}									// and copy the first byte into the signal buffer
		}
	}

}