/* Readout routine with byte overflow protection */
void Hardware::ADC_ReadData(unsigned int channel, unsigned char *signal, unsigned int int_count, bool invert)
{
	channel--;										// convert real channel number to logical channel 
	int_count++;										// because of below pre-decrement

	volatile unsigned long* regAddr = (unsigned long *) RegADC[channel];


	// delay compensation in fast acquisition TB (1 GSa/S) 
	if(MainTimebase < 8)
	{	
		signal += _ChannelDelay[channel];						// shift buffer address (1 byte = 1nS)
	}


	// The Signal comes head over heals -> so we have to invert it for correct
	// display. Therefor we only have to adjust the virtual zero in inverted mode.
	if (invert)
	{
		unsigned char adc_v_zero = _ADC_VirtualZero[channel] << 1;

		if (MainTimebase < 11 || USTB_Mode != USTB_OFF)					// Highspeed  -> 16KB memory and all 4 ADC
		{ 
			unsigned char byte[4];
			unsigned long *uint32_signal = (unsigned long *) signal;		// point 32 bit integer aligned to the signal buffer
			unsigned long *uint32_buffer = (unsigned long *) &byte[0];		// point 32 bit integer aligned to the readout buffer

			char offset1 = _ADC_Offset[channel][0];
			char offset2 = _ADC_Offset[channel][1];
			char offset3 = _ADC_Offset[channel][2];
			char offset4 = _ADC_Offset[channel][3];

			// read byte data integer aligned from FPGA register
			while (--int_count)
			{
				*uint32_buffer = *regAddr;					// read register and invert all bytes
				byte[0] += offset1 + adc_v_zero;				// make correction in byte format to avoid overflow
				byte[1] += offset2 + adc_v_zero;
				byte[2] += offset3 + adc_v_zero;
				byte[3] += offset4 + adc_v_zero;
				*uint32_signal++ = *uint32_buffer;				// copy bytes integer aligned to the signal buffer
			}	
		}
		else										// Lowspeed -> 4kB memory and only one ADC
		{
			char offset = _ADC_Offset[channel][0];

			// read byte data integer aligned from FPGA register
			while (--int_count)
			{
				*signal++ = adc_v_zero + (unsigned char) *regAddr + offset;	// make offset correction for all 4 bytes in one step
			}									// and copy the first byte into the signal buffer
		}
	}
	else
	{
		if (MainTimebase < 11 || USTB_Mode != USTB_OFF)					// Highspeed  -> 16KB memory and all 4 ADC
		{ 
			unsigned char byte[4];
			unsigned long *uint32_signal = (unsigned long *) signal;		// point 32 bit integer aligned to the signal buffer
			unsigned long *uint32_buffer = (unsigned long *) &byte[0];		// point 32 bit integer aligned to the readout buffer

			char offset1 = _ADC_Offset[channel][0];
			char offset2 = _ADC_Offset[channel][1];
			char offset3 = _ADC_Offset[channel][2];
			char offset4 = _ADC_Offset[channel][3];

			// read byte data integer aligned from FPGA register
			while (--int_count)
			{
				*uint32_buffer = ~*regAddr;					// read register and invert all bytes
				byte[0] -= offset1;						// make correction in byte format to avoid overflow
				byte[1] -= offset2;
				byte[2] -= offset3;
				byte[3] -= offset4;

				*uint32_signal++ = *uint32_buffer;				// copy bytes integer aligned to the signal buffer
			}	
		}
		else										// Lowspeed -> 4kB memory and only one ADC
		{
			char offset = _ADC_Offset[channel][0];
			// read byte data integer aligned from FPGA register
			while (--int_count)
			{
				*signal++ = ~(unsigned char) *regAddr - offset; 		// make offset correction for all 4 bytes in one step
			}									// and copy the first byte into the signal buffer
		}
	}

}