cpldfit: version O.76xd Xilinx Inc.
Fitter Report
Design Name: Main Date: 3- 2-2012, 12:25PM
Device Used: XC2C256-7-TQ144
Fitting Status: Successful
************************* Mapped Resource Summary **************************
Macrocells Product Terms Function Block Registers Pins
Used/Tot Used/Tot Inps Used/Tot Used/Tot Used/Tot
48 /256 ( 19%) 103 /896 ( 11%) 87 /640 ( 14%) 31 /256 ( 12%) 31 /118 ( 26%)
** Function Block Resources **
Function Mcells FB Inps Pterms IO CTC CTR CTS CTE
Block Used/Tot Used/Tot Used/Tot Used/Tot Used/Tot Used/Tot Used/Tot Used/Tot
FB1 16/16* 16/40 16/56 0/ 6 1/1* 0/1 0/1 0/1
FB2 6/16 16/40 16/56 0/ 8 1/1* 0/1 0/1 0/1
FB3 0/16 0/40 0/56 0/ 6 0/1 0/1 0/1 0/1
FB4 4/16 7/40 6/56 1/ 8 1/1* 0/1 0/1 0/1
FB5 0/16 0/40 0/56 0/ 5 0/1 0/1 0/1 0/1
FB6 0/16 0/40 0/56 0/ 8 0/1 0/1 0/1 0/1
FB7 0/16 0/40 0/56 0/ 8 0/1 0/1 0/1 0/1
FB8 2/16 6/40 3/56 2/ 8 1/1* 0/1 0/1 0/1
FB9 0/16 0/40 0/56 0/ 8 0/1 0/1 0/1 0/1
FB10 5/16 5/40 6/56 0/ 9 1/1* 0/1 0/1 0/1
FB11 4/16 2/40 4/56 4/ 8 0/1 0/1 0/1 0/1
FB12 0/16 0/40 0/56 0/ 6 0/1 0/1 0/1 0/1
FB13 0/16 0/40 0/56 0/ 8 0/1 0/1 0/1 0/1
FB14 5/16 19/40 16/56 5/ 8 1/1* 0/1 0/1 0/1
FB15 0/16 0/40 0/56 0/ 7 0/1 0/1 0/1 0/1
FB16 6/16 16/40 36/56 6/ 7 0/1 0/1 0/1 0/1
----- ------- ------- ----- --- --- --- ---
Total 48/256 87/640 103/896 18/118 6/16 0/16 0/16 0/16
CTC - Control Term Clock
CTR - Control Term Reset
CTS - Control Term Set
CTE - Control Term Output Enable
* - Resource is exhausted
** Global Control Resources **
GCK GSR GTS DGE
Used/Tot Used/Tot Used/Tot Used/Tot
0/3 1/1 0/4 0/1
Signal 'RST' mapped onto global set/reset net GSR.
** Pin Resources **
Signal Type Required Mapped | Pin Type Used Total
------------------------------------|------------------------------------
Input : 12 12 | I/O : 30 108
Output : 18 18 | GCK/IO : 0 3
Bidirectional : 0 0 | GTS/IO : 0 4
GCK : 0 0 | GSR/IO : 1 1
GTS : 0 0 | CDR/IO : 0 1
GSR : 1 1 | DGE/IO : 0 1
---- ----
Total 31 31
End of Mapped Resource Summary
************************** Errors and Warnings ***************************
WARNING:Cpld - Unable to retrieve the path to the iSE Project Repository. Will
use the default filename of 'Main.ise'.
************************* Summary of Mapped Logic ************************
** 18 Outputs **
Signal Total Total Bank Loc Pin Pin Pin I/O I/O Slew Reg Reg Init
Name Pts Inps No. Type Use STD Style Rate Use State
RD 3 6 2 FB4_3 13 I/O O LVCMOS18 FAST DDFF/S SET
WR 0 0 1 FB8_1 44 I/O O LVCMOS18 FAST
OE 3 6 1 FB8_3 46 I/O O LVCMOS18 FAST DDFF/S SET
Dig<0> 1 2 2 FB11_13 126 I/O O LVCMOS18 FAST
Dig<1> 1 2 2 FB11_14 128 I/O O LVCMOS18 FAST
Dig<2> 1 2 2 FB11_15 129 I/O O LVCMOS18 FAST
Dig<3> 1 2 2 FB11_16 130 I/O O LVCMOS18 FAST
LEDs<0> 1 1 1 FB14_4 69 I/O O LVCMOS18 FAST
LEDs<1> 1 1 1 FB14_6 68 I/O O LVCMOS18 FAST
LEDs<2> 3 6 1 FB14_13 66 I/O O LVCMOS18 FAST DDFF RESET
LEDs<3> 3 6 1 FB14_14 64 I/O O LVCMOS18 FAST DDFF RESET
Seg<6> 9 13 1 FB14_16 61 I/O O LVCMOS18 FAST
Seg<2> 7 13 1 FB16_5 60 I/O O LVCMOS18 FAST
Seg<3> 7 15 1 FB16_11 58 I/O O LVCMOS18 FAST
Seg<4> 6 12 1 FB16_12 57 I/O O LVCMOS18 FAST
Seg<0> 6 12 1 FB16_13 56 I/O O LVCMOS18 FAST
Seg<5> 9 14 1 FB16_15 54 I/O O LVCMOS18 FAST
Seg<1> 8 14 1 FB16_16 53 I/O O LVCMOS18 FAST
** 30 Buried Nodes **
Signal Total Total Loc Reg Reg Init
Name Pts Inps Use State
CNT<9> 2 10 FB1_1 TDFF/S SET
CNT<8> 2 9 FB1_2 TDFF/S SET
CNT<15> 2 16 FB1_3 TDFF/S SET
CNT<14> 2 15 FB1_4 TDFF/S SET
CNT<7> 2 8 FB1_5 TDFF/S SET
CNT<13> 2 14 FB1_6 TDFF/S SET
CNT<6> 2 7 FB1_7 TDFF/S SET
CNT<5> 2 6 FB1_8 TDFF/S SET
CNT<4> 2 5 FB1_9 TDFF/S SET
CNT<3> 2 4 FB1_10 TDFF/S SET
CNT<2> 2 3 FB1_11 TDFF/S SET
CNT<12> 2 13 FB1_12 TDFF/S SET
CNT<11> 2 12 FB1_13 TDFF/S SET
CNT<10> 2 11 FB1_14 TDFF/S SET
CNT<1> 2 2 FB1_15 TDFF/S SET
CNT<0> 1 1 FB1_16 TDFF/S SET
N_PZ_255 1 3 FB2_7
Dbg_1<0> 5 6 FB2_8 TDFF RESET
Dbg_1<1> 3 5 FB2_9 DDFF RESET
Dbg_1<2> 3 4 FB2_10 DDFF RESET
N_PZ_279 3 13 FB2_11
N_PZ_256 3 13 FB2_16
Dbg_3<3> 2 5 FB4_6 DDEFF RESET
Dbg_3<2> 2 5 FB4_12 DDEFF RESET
Dbg_3<1> 2 5 FB4_14 DDEFF RESET
Dbg_4<1> 2 5 FB10_1 DDEFF RESET
Dbg_4<0> 2 5 FB10_2 DDEFF RESET
Dbg_4<3> 2 5 FB10_3 DDEFF RESET
Dbg_4<2> 2 5 FB10_4 DDEFF RESET
Dbg_3<0> 2 5 FB10_5 DDEFF RESET
** 13 Inputs **
Signal Bank Loc Pin Pin Pin I/O I/O
Name No. Type Use STD Style
RST 2 FB1_3 143 GSR/I/O GSR LVCMOS18 KPR
TXE 2 FB4_4 14 I/O I LVCMOS18 KPR
RXF 2 FB4_5 15 I/O I LVCMOS18 KPR
FIFO_Data<7> 2 FB4_6 16 I/O I LVCMOS18 KPR
FIFO_Data<6> 2 FB4_12 17 I/O I LVCMOS18 KPR
FIFO_Data<5> 2 FB4_14 18 I/O I LVCMOS18 KPR
CLK 1 FB8_2 45 I/O I LVCMOS18 S/KPR
FIFO_Data<1> 2 FB10_1 111 I/O I LVCMOS18 KPR
FIFO_Data<0> 2 FB10_2 110 I/O I LVCMOS18 KPR
FIFO_Data<3> 2 FB10_3 107 I/O I LVCMOS18 KPR
FIFO_Data<2> 2 FB10_4 106 I/O I LVCMOS18 KPR
FIFO_Data<4> 2 FB10_5 105 I/O I LVCMOS18 KPR
STA 2 FB12_15 94 I/O I LVCMOS18 KPR
Legend:
Pin No. - ~ - User Assigned
I/O Style - OD - OpenDrain
- PU - Pullup
- KPR - Keeper
- S - SchmittTrigger
- DG - DataGate
Reg Use - LATCH - Transparent latch
- DFF - D-flip-flop
- DEFF - D-flip-flop with clock enable
- TFF - T-flip-flop
- TDFF - Dual-edge-triggered T-flip-flop
- DDFF - Dual-edge-triggered flip-flop
- DDEFF - Dual-edge-triggered flip-flop with clock enable
/S (after any above flop/latch type) indicates initial state is Set
************************** Function Block Details ************************
Legend:
Total Pt - Total product terms used by the macrocell signal
Loc - Location where logic was mapped in device
Pin Type/Use - I - Input GCK - Global clock
O - Output GTS - Global Output Enable
(b) - Buried macrocell GSR - Global Set/Reset
VRF - Vref
Pin No. - ~ - User Assigned
*********************************** FB1 ***********************************
This function block is part of I/O Bank number: 2
Number of function block inputs used/remaining: 16/24
Number of function block control terms used/remaining: 1/3
Number of PLA product terms used/remaining: 16/40
Signal Total Loc Pin Pin Pin CTC CTR CTS CTE
Name Pt No. Type Use
CNT<9> 2 FB1_1 (b) (b) +
CNT<8> 2 FB1_2 (b) (b) +
CNT<15> 2 FB1_3 143 GSR/I/O GSR +
CNT<14> 2 FB1_4 142 I/O (b) +
CNT<7> 2 FB1_5 (b) (b) +
CNT<13> 2 FB1_6 140 I/O (b) +
CNT<6> 2 FB1_7 (b) (b) +
CNT<5> 2 FB1_8 (b) (b) +
CNT<4> 2 FB1_9 (b) (b) +
CNT<3> 2 FB1_10 (b) (b) +
CNT<2> 2 FB1_11 (b) (b) +
CNT<12> 2 FB1_12 139 I/O (b) +
CNT<11> 2 FB1_13 138 I/O (b) +
CNT<10> 2 FB1_14 137 I/O (b) +
CNT<1> 2 FB1_15 (b) (b) +
CNT<0> 1 FB1_16 (b) (b) +
Signals Used by Logic in Function Block
1: CLK 7: CNT<14> 12: CNT<5>
2: CNT<0> 8: CNT<1> 13: CNT<6>
3: CNT<10> 9: CNT<2> 14: CNT<7>
4: CNT<11> 10: CNT<3> 15: CNT<8>
5: CNT<12> 11: CNT<4> 16: CNT<9>
6: CNT<13>
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
CNT<9> XX.....XXXXXXXX......................... 10
CNT<8> XX.....XXXXXXX.......................... 9
CNT<15> XXXXXXXXXXXXXXXX........................ 16
CNT<14> XXXXXX.XXXXXXXXX........................ 15
CNT<7> XX.....XXXXXX........................... 8
CNT<13> XXXXX..XXXXXXXXX........................ 14
CNT<6> XX.....XXXXX............................ 7
CNT<5> XX.....XXXX............................. 6
CNT<4> XX.....XXX.............................. 5
CNT<3> XX.....XX............................... 4
CNT<2> XX.....X................................ 3
CNT<12> XXXX...XXXXXXXXX........................ 13
CNT<11> XXX....XXXXXXXXX........................ 12
CNT<10> XX.....XXXXXXXXX........................ 11
CNT<1> XX...................................... 2
CNT<0> X....................................... 1
0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB2 ***********************************
This function block is part of I/O Bank number: 2
Number of function block inputs used/remaining: 16/24
Number of function block control terms used/remaining: 1/3
Number of PLA product terms used/remaining: 16/40
Signal Total Loc Pin Pin Pin CTC CTR CTS CTE
Name Pt No. Type Use
(unused) 0 FB2_1 2 GTS/I/O
(unused) 0 FB2_2 (b)
(unused) 0 FB2_3 3 GTS/I/O
(unused) 0 FB2_4 4 I/O
(unused) 0 FB2_5 5 GTS/I/O
(unused) 0 FB2_6 (b)
N_PZ_255 1 FB2_7 (b) (b)
Dbg_1<0> 5 FB2_8 (b) (b) +
Dbg_1<1> 3 FB2_9 (b) (b) +
Dbg_1<2> 3 FB2_10 (b) (b) +
N_PZ_279 3 FB2_11 (b) (b)
(unused) 0 FB2_12 6 GTS/I/O
(unused) 0 FB2_13 7 I/O
(unused) 0 FB2_14 9 I/O
(unused) 0 FB2_15 10 I/O
N_PZ_256 3 FB2_16 (b) (b)
Signals Used by Logic in Function Block
1: CLK 7: Dbg_3<0> 12: Dbg_4<1>
2: CNT<14> 8: Dbg_3<1> 13: Dbg_4<2>
3: CNT<15> 9: Dbg_3<2> 14: Dbg_4<3>
4: Dbg_1<0> 10: Dbg_3<3> 15: RXF
5: Dbg_1<1> 11: Dbg_4<0> 16: STA
6: Dbg_1<2>
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
N_PZ_255 ...XXX.................................. 3
Dbg_1<0> X..XXX........XX........................ 6
Dbg_1<1> X..XXX........X......................... 5
Dbg_1<2> X..XXX.................................. 4
N_PZ_279 .XXXXXXXXXXXXX.......................... 13
N_PZ_256 .XXXXXXXXXXXXX.......................... 13
0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB3 ***********************************
This function block is part of I/O Bank number: 2
Number of function block inputs used/remaining: 0/40
Number of function block control terms used/remaining: 0/4
Number of PLA product terms used/remaining: 0/56
Signal Total Loc Pin Pin Pin CTC CTR CTS CTE
Name Pt No. Type Use
(unused) 0 FB3_1 136 I/O
(unused) 0 FB3_2 135 I/O
(unused) 0 FB3_3 134 I/O
(unused) 0 FB3_4 (b)
(unused) 0 FB3_5 133 I/O
(unused) 0 FB3_6 (b)
(unused) 0 FB3_7 (b)
(unused) 0 FB3_8 (b)
(unused) 0 FB3_9 (b)
(unused) 0 FB3_10 (b)
(unused) 0 FB3_11 (b)
(unused) 0 FB3_12 (b)
(unused) 0 FB3_13 (b)
(unused) 0 FB3_14 132 I/O
(unused) 0 FB3_15 (b)
(unused) 0 FB3_16 131 I/O
*********************************** FB4 ***********************************
This function block is part of I/O Bank number: 2
Number of function block inputs used/remaining: 7/33
Number of function block control terms used/remaining: 1/3
Number of PLA product terms used/remaining: 6/50
Signal Total Loc Pin Pin Pin CTC CTR CTS CTE
Name Pt No. Type Use
(unused) 0 FB4_1 11 I/O
(unused) 0 FB4_2 12 I/O
RD 3 FB4_3 13 I/O O +
(unused) 0 FB4_4 14 I/O I
(unused) 0 FB4_5 15 I/O I
Dbg_3<3> 2 FB4_6 16 I/O I +
(unused) 0 FB4_7 (b)
(unused) 0 FB4_8 (b)
(unused) 0 FB4_9 (b)
(unused) 0 FB4_10 (b)
(unused) 0 FB4_11 (b)
Dbg_3<2> 2 FB4_12 17 I/O I +
(unused) 0 FB4_13 (b)
Dbg_3<1> 2 FB4_14 18 I/O I +
(unused) 0 FB4_15 (b)
(unused) 0 FB4_16 (b)
Signals Used by Logic in Function Block
1: CLK 4: Dbg_1<2> 6: RD
2: Dbg_1<0> 5: N_PZ_255 7: RXF
3: Dbg_1<1>
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
RD XXXXXX.................................. 6
0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB5 ***********************************
This function block is part of I/O Bank number: 1
Number of function block inputs used/remaining: 0/40
Number of function block control terms used/remaining: 0/4
Number of PLA product terms used/remaining: 0/56
Signal Total Loc Pin Pin Pin CTC CTR CTS CTE
Name Pt No. Type Use
(unused) 0 FB5_1 (b)
(unused) 0 FB5_2 33 I/O
(unused) 0 FB5_3 (b)
(unused) 0 FB5_4 32 GCK/I/O
(unused) 0 FB5_5 31 I/O
(unused) 0 FB5_6 30 GCK/I/O
(unused) 0 FB5_7 (b)
(unused) 0 FB5_8 (b)
(unused) 0 FB5_9 (b)
(unused) 0 FB5_10 (b)
(unused) 0 FB5_11 (b)
(unused) 0 FB5_12 (b)
(unused) 0 FB5_13 (b)
(unused) 0 FB5_14 28 I/O
(unused) 0 FB5_15 (b)
(unused) 0 FB5_16 (b)
*********************************** FB6 ***********************************
This function block is part of I/O Bank number: 1
Number of function block inputs used/remaining: 0/40
Number of function block control terms used/remaining: 0/4
Number of PLA product terms used/remaining: 0/56
Signal Total Loc Pin Pin Pin CTC CTR CTS CTE
Name Pt No. Type Use
(unused) 0 FB6_1 34 I/O
(unused) 0 FB6_2 35 CDR/I/O
(unused) 0 FB6_3 (b)
(unused) 0 FB6_4 38 GCK/I/O
(unused) 0 FB6_5 (b)
(unused) 0 FB6_6 (b)
(unused) 0 FB6_7 (b)
(unused) 0 FB6_8 (b)
(unused) 0 FB6_9 (b)
(unused) 0 FB6_10 (b)
(unused) 0 FB6_11 (b)
(unused) 0 FB6_12 39 DGE/I/O
(unused) 0 FB6_13 40 I/O
(unused) 0 FB6_14 41 I/O
(unused) 0 FB6_15 42 I/O
(unused) 0 FB6_16 43 I/O
*********************************** FB7 ***********************************
This function block is part of I/O Bank number: 1
Number of function block inputs used/remaining: 0/40
Number of function block control terms used/remaining: 0/4
Number of PLA product terms used/remaining: 0/56
Signal Total Loc Pin Pin Pin CTC CTR CTS CTE
Name Pt No. Type Use
(unused) 0 FB7_1 (b)
(unused) 0 FB7_2 (b)
(unused) 0 FB7_3 (b)
(unused) 0 FB7_4 (b)
(unused) 0 FB7_5 26 I/O
(unused) 0 FB7_6 25 I/O
(unused) 0 FB7_7 (b)
(unused) 0 FB7_8 (b)
(unused) 0 FB7_9 (b)
(unused) 0 FB7_10 (b)
(unused) 0 FB7_11 24 I/O
(unused) 0 FB7_12 23 I/O
(unused) 0 FB7_13 22 I/O
(unused) 0 FB7_14 21 I/O
(unused) 0 FB7_15 20 I/O
(unused) 0 FB7_16 19 I/O
*********************************** FB8 ***********************************
This function block is part of I/O Bank number: 1
Number of function block inputs used/remaining: 6/34
Number of function block control terms used/remaining: 1/3
Number of PLA product terms used/remaining: 3/53
Signal Total Loc Pin Pin Pin CTC CTR CTS CTE
Name Pt No. Type Use
WR 0 FB8_1 44 I/O O
(unused) 0 FB8_2 45 I/O I
OE 3 FB8_3 46 I/O O +
(unused) 0 FB8_4 (b)
(unused) 0 FB8_5 48 I/O
(unused) 0 FB8_6 49 I/O
(unused) 0 FB8_7 (b)
(unused) 0 FB8_8 (b)
(unused) 0 FB8_9 (b)
(unused) 0 FB8_10 (b)
(unused) 0 FB8_11 50 I/O
(unused) 0 FB8_12 51 I/O
(unused) 0 FB8_13 52 I/O
(unused) 0 FB8_14 (b)
(unused) 0 FB8_15 (b)
(unused) 0 FB8_16 (b)
Signals Used by Logic in Function Block
1: CLK 3: Dbg_1<1> 5: N_PZ_255
2: Dbg_1<0> 4: Dbg_1<2> 6: OE
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
WR ........................................ 0
OE XXXXXX.................................. 6
0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB9 ***********************************
This function block is part of I/O Bank number: 2
Number of function block inputs used/remaining: 0/40
Number of function block control terms used/remaining: 0/4
Number of PLA product terms used/remaining: 0/56
Signal Total Loc Pin Pin Pin CTC CTR CTS CTE
Name Pt No. Type Use
(unused) 0 FB9_1 112 I/O
(unused) 0 FB9_2 113 I/O
(unused) 0 FB9_3 (b)
(unused) 0 FB9_4 114 I/O
(unused) 0 FB9_5 (b)
(unused) 0 FB9_6 115 I/O
(unused) 0 FB9_7 (b)
(unused) 0 FB9_8 (b)
(unused) 0 FB9_9 (b)
(unused) 0 FB9_10 (b)
(unused) 0 FB9_11 (b)
(unused) 0 FB9_12 116 I/O
(unused) 0 FB9_13 117 I/O
(unused) 0 FB9_14 118 I/O
(unused) 0 FB9_15 119 I/O
(unused) 0 FB9_16 (b)
*********************************** FB10 ***********************************
This function block is part of I/O Bank number: 2
Number of function block inputs used/remaining: 5/35
Number of function block control terms used/remaining: 1/3
Number of PLA product terms used/remaining: 6/50
Signal Total Loc Pin Pin Pin CTC CTR CTS CTE
Name Pt No. Type Use
Dbg_4<1> 2 FB10_1 111 I/O I +
Dbg_4<0> 2 FB10_2 110 I/O I +
Dbg_4<3> 2 FB10_3 107 I/O I +
Dbg_4<2> 2 FB10_4 106 I/O I +
Dbg_3<0> 2 FB10_5 105 I/O I +
(unused) 0 FB10_6 104 I/O
(unused) 0 FB10_7 (b)
(unused) 0 FB10_8 (b)
(unused) 0 FB10_9 (b)
(unused) 0 FB10_10 (b)
(unused) 0 FB10_11 (b)
(unused) 0 FB10_12 103 I/O
(unused) 0 FB10_13 (b)
(unused) 0 FB10_14 102 I/O
(unused) 0 FB10_15 (b)
(unused) 0 FB10_16 101 I/O
Signals Used by Logic in Function Block
1: CLK 3: Dbg_1<1> 5: RXF
2: Dbg_1<0> 4: Dbg_1<2>
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB11 ***********************************
This function block is part of I/O Bank number: 2
Number of function block inputs used/remaining: 2/38
Number of function block control terms used/remaining: 0/4
Number of PLA product terms used/remaining: 4/52
Signal Total Loc Pin Pin Pin CTC CTR CTS CTE
Name Pt No. Type Use
(unused) 0 FB11_1 (b)
(unused) 0 FB11_2 (b)
(unused) 0 FB11_3 (b)
(unused) 0 FB11_4 (b)
(unused) 0 FB11_5 120 I/O
(unused) 0 FB11_6 121 I/O
(unused) 0 FB11_7 (b)
(unused) 0 FB11_8 (b)
(unused) 0 FB11_9 (b)
(unused) 0 FB11_10 (b)
(unused) 0 FB11_11 124 I/O
(unused) 0 FB11_12 125 I/O
Dig<0> 1 FB11_13 126 I/O O
Dig<1> 1 FB11_14 128 I/O O
Dig<2> 1 FB11_15 129 I/O O
Dig<3> 1 FB11_16 130 I/O O
Signals Used by Logic in Function Block
1: CNT<14> 2: CNT<15>
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
Dig<0> XX...................................... 2
Dig<1> XX...................................... 2
Dig<2> XX...................................... 2
Dig<3> XX...................................... 2
0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB12 ***********************************
This function block is part of I/O Bank number: 2
Number of function block inputs used/remaining: 0/40
Number of function block control terms used/remaining: 0/4
Number of PLA product terms used/remaining: 0/56
Signal Total Loc Pin Pin Pin CTC CTR CTS CTE
Name Pt No. Type Use
(unused) 0 FB12_1 (b)
(unused) 0 FB12_2 100 I/O
(unused) 0 FB12_3 (b)
(unused) 0 FB12_4 (b)
(unused) 0 FB12_5 (b)
(unused) 0 FB12_6 (b)
(unused) 0 FB12_7 (b)
(unused) 0 FB12_8 (b)
(unused) 0 FB12_9 (b)
(unused) 0 FB12_10 (b)
(unused) 0 FB12_11 98 I/O
(unused) 0 FB12_12 97 I/O
(unused) 0 FB12_13 96 I/O
(unused) 0 FB12_14 95 I/O
(unused) 0 FB12_15 94 I/O I
(unused) 0 FB12_16 (b)
*********************************** FB13 ***********************************
This function block is part of I/O Bank number: 1
Number of function block inputs used/remaining: 0/40
Number of function block control terms used/remaining: 0/4
Number of PLA product terms used/remaining: 0/56
Signal Total Loc Pin Pin Pin CTC CTR CTS CTE
Name Pt No. Type Use
(unused) 0 FB13_1 75 I/O
(unused) 0 FB13_2 76 I/O
(unused) 0 FB13_3 77 I/O
(unused) 0 FB13_4 (b)
(unused) 0 FB13_5 78 I/O
(unused) 0 FB13_6 79 I/O
(unused) 0 FB13_7 (b)
(unused) 0 FB13_8 (b)
(unused) 0 FB13_9 (b)
(unused) 0 FB13_10 (b)
(unused) 0 FB13_11 (b)
(unused) 0 FB13_12 80 I/O
(unused) 0 FB13_13 81 I/O
(unused) 0 FB13_14 82 I/O
(unused) 0 FB13_15 (b)
(unused) 0 FB13_16 (b)
*********************************** FB14 ***********************************
This function block is part of I/O Bank number: 1
Number of function block inputs used/remaining: 19/21
Number of function block control terms used/remaining: 1/3
Number of PLA product terms used/remaining: 16/40
Signal Total Loc Pin Pin Pin CTC CTR CTS CTE
Name Pt No. Type Use
(unused) 0 FB14_1 74 I/O
(unused) 0 FB14_2 71 I/O
(unused) 0 FB14_3 70 I/O
LEDs<0> 1 FB14_4 69 I/O O
(unused) 0 FB14_5 (b)
LEDs<1> 1 FB14_6 68 I/O O
(unused) 0 FB14_7 (b)
(unused) 0 FB14_8 (b)
(unused) 0 FB14_9 (b)
(unused) 0 FB14_10 (b)
(unused) 0 FB14_11 (b)
(unused) 0 FB14_12 (b)
LEDs<2> 3 FB14_13 66 I/O O +
LEDs<3> 3 FB14_14 64 I/O O +
(unused) 0 FB14_15 (b)
Seg<6> 9 FB14_16 61 I/O O
Signals Used by Logic in Function Block
1: CLK 8: Dbg_3<1> 14: Dbg_4<3>
2: CNT<14> 9: Dbg_3<2> 15: N_PZ_255
3: CNT<15> 10: Dbg_3<3> 16: OE
4: Dbg_1<0> 11: Dbg_4<0> 17: RD
5: Dbg_1<1> 12: Dbg_4<1> 18: RXF
6: Dbg_1<2> 13: Dbg_4<2> 19: TXE
7: Dbg_3<0>
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
LEDs<0> ..................X..................... 1
LEDs<1> .................X...................... 1
LEDs<2> X..XXX........XX........................ 6
LEDs<3> X..XXX........X.X....................... 6
Seg<6> .XXXXXXXXXXXXX.......................... 13
0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB15 ***********************************
This function block is part of I/O Bank number: 1
Number of function block inputs used/remaining: 0/40
Number of function block control terms used/remaining: 0/4
Number of PLA product terms used/remaining: 0/56
Signal Total Loc Pin Pin Pin CTC CTR CTS CTE
Name Pt No. Type Use
(unused) 0 FB15_1 (b)
(unused) 0 FB15_2 83 I/O
(unused) 0 FB15_3 (b)
(unused) 0 FB15_4 (b)
(unused) 0 FB15_5 (b)
(unused) 0 FB15_6 (b)
(unused) 0 FB15_7 (b)
(unused) 0 FB15_8 (b)
(unused) 0 FB15_9 (b)
(unused) 0 FB15_10 (b)
(unused) 0 FB15_11 85 I/O
(unused) 0 FB15_12 86 I/O
(unused) 0 FB15_13 87 I/O
(unused) 0 FB15_14 88 I/O
(unused) 0 FB15_15 91 I/O
(unused) 0 FB15_16 92 I/O
*********************************** FB16 ***********************************
This function block is part of I/O Bank number: 1
Number of function block inputs used/remaining: 16/24
Number of function block control terms used/remaining: 0/4
Number of PLA product terms used/remaining: 36/20
Signal Total Loc Pin Pin Pin CTC CTR CTS CTE
Name Pt No. Type Use
(unused) 0 FB16_1 (b)
(unused) 0 FB16_2 (b)
(unused) 0 FB16_3 (b)
(unused) 0 FB16_4 (b)
Seg<2> 7 FB16_5 60 I/O O
(unused) 0 FB16_6 59 I/O
(unused) 0 FB16_7 (b)
(unused) 0 FB16_8 (b)
(unused) 0 FB16_9 (b)
(unused) 0 FB16_10 (b)
Seg<3> 7 FB16_11 58 I/O O
Seg<4> 6 FB16_12 57 I/O O
Seg<0> 6 FB16_13 56 I/O O
(unused) 0 FB16_14 (b)
Seg<5> 9 FB16_15 54 I/O O
Seg<1> 8 FB16_16 53 I/O O
Signals Used by Logic in Function Block
1: CNT<14> 7: Dbg_3<1> 12: Dbg_4<2>
2: CNT<15> 8: Dbg_3<2> 13: Dbg_4<3>
3: Dbg_1<0> 9: Dbg_3<3> 14: N_PZ_255
4: Dbg_1<1> 10: Dbg_4<0> 15: N_PZ_256
5: Dbg_1<2> 11: Dbg_4<1> 16: N_PZ_279
6: Dbg_3<0>
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
Seg<2> XXXXXXXXXXXXX........................... 13
Seg<3> XXXXXXXXXXXXX.XX........................ 15
Seg<4> XXX..XXXXXXXX..X........................ 12
Seg<0> XX...XXXXXXXX.XX........................ 12
Seg<5> XXXXXXXXXXXXX.X......................... 14
Seg<1> XXX.XXXXXXXXXX.X........................ 14
0----+----1----+----2----+----3----+----4
0 0 0 0
******************************* Equations ********************************
********** Mapped Logic **********
FTDCPE_CNT0: FTDCPE port map (CNT(0),'0',CLK,'0',NOT RST,'1');
FTDCPE_CNT1: FTDCPE port map (CNT(1),CNT(0),CLK,'0',NOT RST,'1');
FTDCPE_CNT2: FTDCPE port map (CNT(2),CNT_T(2),CLK,'0',NOT RST,'1');
CNT_T(2) <= (CNT(0) AND CNT(1));
FTDCPE_CNT3: FTDCPE port map (CNT(3),CNT_T(3),CLK,'0',NOT RST,'1');
CNT_T(3) <= (CNT(0) AND CNT(1) AND CNT(2));
FTDCPE_CNT4: FTDCPE port map (CNT(4),CNT_T(4),CLK,'0',NOT RST,'1');
CNT_T(4) <= (CNT(0) AND CNT(1) AND CNT(2) AND CNT(3));
FTDCPE_CNT5: FTDCPE port map (CNT(5),CNT_T(5),CLK,'0',NOT RST,'1');
CNT_T(5) <= (CNT(0) AND CNT(1) AND CNT(2) AND CNT(3) AND CNT(4));
FTDCPE_CNT6: FTDCPE port map (CNT(6),CNT_T(6),CLK,'0',NOT RST,'1');
CNT_T(6) <= (CNT(0) AND CNT(1) AND CNT(2) AND CNT(3) AND CNT(4) AND
CNT(5));
FTDCPE_CNT7: FTDCPE port map (CNT(7),CNT_T(7),CLK,'0',NOT RST,'1');
CNT_T(7) <= (CNT(0) AND CNT(1) AND CNT(2) AND CNT(3) AND CNT(4) AND
CNT(5) AND CNT(6));
FTDCPE_CNT8: FTDCPE port map (CNT(8),CNT_T(8),CLK,'0',NOT RST,'1');
CNT_T(8) <= (CNT(0) AND CNT(1) AND CNT(2) AND CNT(3) AND CNT(4) AND
CNT(5) AND CNT(6) AND CNT(7));
FTDCPE_CNT9: FTDCPE port map (CNT(9),CNT_T(9),CLK,'0',NOT RST,'1');
CNT_T(9) <= (CNT(0) AND CNT(1) AND CNT(2) AND CNT(3) AND CNT(4) AND
CNT(5) AND CNT(6) AND CNT(7) AND CNT(8));
FTDCPE_CNT10: FTDCPE port map (CNT(10),CNT_T(10),CLK,'0',NOT RST,'1');
CNT_T(10) <= (CNT(0) AND CNT(1) AND CNT(2) AND CNT(3) AND CNT(4) AND
CNT(5) AND CNT(6) AND CNT(7) AND CNT(8) AND CNT(9));
FTDCPE_CNT11: FTDCPE port map (CNT(11),CNT_T(11),CLK,'0',NOT RST,'1');
CNT_T(11) <= (CNT(0) AND CNT(10) AND CNT(1) AND CNT(2) AND CNT(3) AND
CNT(4) AND CNT(5) AND CNT(6) AND CNT(7) AND CNT(8) AND CNT(9));
FTDCPE_CNT12: FTDCPE port map (CNT(12),CNT_T(12),CLK,'0',NOT RST,'1');
CNT_T(12) <= (CNT(0) AND CNT(10) AND CNT(1) AND CNT(2) AND CNT(3) AND
CNT(4) AND CNT(5) AND CNT(6) AND CNT(7) AND CNT(8) AND CNT(9) AND
CNT(11));
FTDCPE_CNT13: FTDCPE port map (CNT(13),CNT_T(13),CLK,'0',NOT RST,'1');
CNT_T(13) <= (CNT(0) AND CNT(10) AND CNT(1) AND CNT(2) AND CNT(3) AND
CNT(4) AND CNT(5) AND CNT(6) AND CNT(7) AND CNT(8) AND CNT(9) AND
CNT(11) AND CNT(12));
FTDCPE_CNT14: FTDCPE port map (CNT(14),CNT_T(14),CLK,'0',NOT RST,'1');
CNT_T(14) <= (CNT(0) AND CNT(10) AND CNT(1) AND CNT(2) AND CNT(3) AND
CNT(4) AND CNT(5) AND CNT(6) AND CNT(7) AND CNT(8) AND CNT(9) AND
CNT(11) AND CNT(12) AND CNT(13));
FTDCPE_CNT15: FTDCPE port map (CNT(15),CNT_T(15),CLK,'0',NOT RST,'1');
CNT_T(15) <= (CNT(0) AND CNT(14) AND CNT(10) AND CNT(1) AND CNT(2) AND
CNT(3) AND CNT(4) AND CNT(5) AND CNT(6) AND CNT(7) AND CNT(8) AND
CNT(9) AND CNT(11) AND CNT(12) AND CNT(13));
FTDCPE_Dbg_10: FTDCPE port map (Dbg_1(0),Dbg_1_T(0),CLK,NOT RST,'0','1');
Dbg_1_T(0) <= NOT (((RXF AND Dbg_1(0) AND NOT Dbg_1(1))
OR (NOT RXF AND NOT Dbg_1(1) AND Dbg_1(2))
OR (NOT Dbg_1(0) AND Dbg_1(1) AND Dbg_1(2))
OR (NOT Dbg_1(0) AND NOT Dbg_1(1) AND NOT Dbg_1(2) AND STA)));
FDDCPE_Dbg_11: FDDCPE port map (Dbg_1(1),Dbg_1_D(1),CLK,NOT RST,'0','1');
Dbg_1_D(1) <= ((NOT Dbg_1(0) AND Dbg_1(1) AND NOT Dbg_1(2))
OR (NOT RXF AND Dbg_1(0) AND NOT Dbg_1(1) AND NOT Dbg_1(2)));
FDDCPE_Dbg_12: FDDCPE port map (Dbg_1(2),Dbg_1_D(2),CLK,NOT RST,'0','1');
Dbg_1_D(2) <= ((Dbg_1(0) AND Dbg_1(1) AND NOT Dbg_1(2))
OR (NOT Dbg_1(0) AND NOT Dbg_1(1) AND Dbg_1(2)));
FDDCPE_Dbg_30: FDDCPE port map (Dbg_3(0),FIFO_Data(4),CLK,NOT RST,'0',Dbg_3_CE(0));
Dbg_3_CE(0) <= (NOT RXF AND NOT Dbg_1(0) AND NOT Dbg_1(1) AND Dbg_1(2));
FDDCPE_Dbg_31: FDDCPE port map (Dbg_3(1),FIFO_Data(5),CLK,NOT RST,'0',Dbg_3_CE(1));
Dbg_3_CE(1) <= (NOT RXF AND NOT Dbg_1(0) AND NOT Dbg_1(1) AND Dbg_1(2));
FDDCPE_Dbg_32: FDDCPE port map (Dbg_3(2),FIFO_Data(6),CLK,NOT RST,'0',Dbg_3_CE(2));
Dbg_3_CE(2) <= (NOT RXF AND NOT Dbg_1(0) AND NOT Dbg_1(1) AND Dbg_1(2));
FDDCPE_Dbg_33: FDDCPE port map (Dbg_3(3),FIFO_Data(7),CLK,NOT RST,'0',Dbg_3_CE(3));
Dbg_3_CE(3) <= (NOT RXF AND NOT Dbg_1(0) AND NOT Dbg_1(1) AND Dbg_1(2));
FDDCPE_Dbg_40: FDDCPE port map (Dbg_4(0),FIFO_Data(0),CLK,NOT RST,'0',Dbg_4_CE(0));
Dbg_4_CE(0) <= (NOT RXF AND NOT Dbg_1(0) AND NOT Dbg_1(1) AND Dbg_1(2));
FDDCPE_Dbg_41: FDDCPE port map (Dbg_4(1),FIFO_Data(1),CLK,NOT RST,'0',Dbg_4_CE(1));
Dbg_4_CE(1) <= (NOT RXF AND NOT Dbg_1(0) AND NOT Dbg_1(1) AND Dbg_1(2));
FDDCPE_Dbg_42: FDDCPE port map (Dbg_4(2),FIFO_Data(2),CLK,NOT RST,'0',Dbg_4_CE(2));
Dbg_4_CE(2) <= (NOT RXF AND NOT Dbg_1(0) AND NOT Dbg_1(1) AND Dbg_1(2));
FDDCPE_Dbg_43: FDDCPE port map (Dbg_4(3),FIFO_Data(3),CLK,NOT RST,'0',Dbg_4_CE(3));
Dbg_4_CE(3) <= (NOT RXF AND NOT Dbg_1(0) AND NOT Dbg_1(1) AND Dbg_1(2));
Dig(0) <= NOT ((CNT(15) AND CNT(14)));
Dig(1) <= NOT ((CNT(15) AND NOT CNT(14)));
Dig(2) <= NOT ((NOT CNT(15) AND CNT(14)));
Dig(3) <= NOT ((NOT CNT(15) AND NOT CNT(14)));
LEDs(0) <= NOT TXE;
LEDs(1) <= NOT RXF;
FDDCPE_LEDs2: FDDCPE port map (LEDs(2),LEDs_D(2),CLK,NOT RST,'0','1');
LEDs_D(2) <= ((NOT OE AND NOT N_PZ_255)
OR (NOT Dbg_1(0) AND Dbg_1(1) AND NOT Dbg_1(2)));
FDDCPE_LEDs3: FDDCPE port map (LEDs(3),LEDs_D(3),CLK,NOT RST,'0','1');
LEDs_D(3) <= ((NOT N_PZ_255 AND NOT RD)
OR (Dbg_1(0) AND Dbg_1(1) AND NOT Dbg_1(2)));
N_PZ_255 <= (Dbg_1(0) AND NOT Dbg_1(1) AND Dbg_1(2));
N_PZ_256 <= ((NOT CNT(15) AND NOT CNT(14) AND Dbg_1(0) AND NOT Dbg_1(1) AND
NOT Dbg_1(2))
OR (CNT(15) AND CNT(14) AND Dbg_4(0) AND NOT Dbg_4(1) AND
NOT Dbg_4(2) AND NOT Dbg_4(3))
OR (CNT(15) AND NOT CNT(14) AND Dbg_3(0) AND NOT Dbg_3(1) AND
NOT Dbg_3(2) AND NOT Dbg_3(3)));
N_PZ_279 <= ((NOT CNT(15) AND NOT CNT(14) AND NOT Dbg_1(0) AND NOT Dbg_1(1) AND
Dbg_1(2))
OR (CNT(15) AND CNT(14) AND NOT Dbg_4(0) AND NOT Dbg_4(1) AND
Dbg_4(2) AND NOT Dbg_4(3))
OR (CNT(15) AND NOT CNT(14) AND NOT Dbg_3(0) AND NOT Dbg_3(1) AND
Dbg_3(2) AND NOT Dbg_3(3)));
FDDCPE_OE: FDDCPE port map (OE,OE_D,CLK,'0',NOT RST,'1');
OE_D <= NOT (((NOT OE AND NOT N_PZ_255)
OR (NOT Dbg_1(0) AND Dbg_1(1) AND NOT Dbg_1(2))));
FDDCPE_RD: FDDCPE port map (RD,RD_D,CLK,'0',NOT RST,'1');
RD_D <= NOT (((NOT N_PZ_255 AND NOT RD)
OR (Dbg_1(0) AND Dbg_1(1) AND NOT Dbg_1(2))));
Seg(0) <= ((N_PZ_279)
OR (N_PZ_256)
OR (CNT(15) AND CNT(14) AND Dbg_4(0) AND Dbg_4(1) AND
NOT Dbg_4(2) AND Dbg_4(3))
OR (CNT(15) AND CNT(14) AND Dbg_4(0) AND NOT Dbg_4(1) AND
Dbg_4(2) AND Dbg_4(3))
OR (CNT(15) AND NOT CNT(14) AND Dbg_3(0) AND Dbg_3(1) AND
NOT Dbg_3(2) AND Dbg_3(3))
OR (CNT(15) AND NOT CNT(14) AND Dbg_3(0) AND NOT Dbg_3(1) AND
Dbg_3(2) AND Dbg_3(3)));
Seg(1) <= ((NOT CNT(15) AND NOT CNT(14) AND N_PZ_255)
OR (CNT(15) AND CNT(14) AND Dbg_4(0) AND Dbg_4(1) AND
Dbg_4(3))
OR (CNT(15) AND CNT(14) AND NOT Dbg_4(0) AND Dbg_4(2) AND
NOT N_PZ_279)
OR (CNT(15) AND NOT CNT(14) AND Dbg_3(0) AND Dbg_3(1) AND
Dbg_3(3))
OR (CNT(15) AND NOT CNT(14) AND NOT Dbg_3(0) AND Dbg_3(2) AND
NOT N_PZ_279)
OR (NOT CNT(15) AND NOT CNT(14) AND NOT Dbg_1(0) AND Dbg_1(2) AND
NOT N_PZ_279)
OR (CNT(15) AND CNT(14) AND NOT Dbg_4(1) AND Dbg_4(2) AND
NOT Dbg_4(3) AND NOT N_PZ_279)
OR (CNT(15) AND NOT CNT(14) AND NOT Dbg_3(1) AND Dbg_3(2) AND
NOT Dbg_3(3) AND NOT N_PZ_279));
Seg(2) <= ((CNT(15) AND CNT(14) AND NOT Dbg_4(0) AND Dbg_4(2) AND
Dbg_4(3))
OR (CNT(15) AND CNT(14) AND Dbg_4(1) AND Dbg_4(2) AND
Dbg_4(3))
OR (CNT(15) AND NOT CNT(14) AND NOT Dbg_3(0) AND Dbg_3(2) AND
Dbg_3(3))
OR (CNT(15) AND NOT CNT(14) AND Dbg_3(1) AND Dbg_3(2) AND
Dbg_3(3))
OR (NOT CNT(15) AND NOT CNT(14) AND NOT Dbg_1(0) AND Dbg_1(1) AND
NOT Dbg_1(2))
OR (CNT(15) AND CNT(14) AND NOT Dbg_4(0) AND Dbg_4(1) AND
NOT Dbg_4(2) AND NOT Dbg_4(3))
OR (CNT(15) AND NOT CNT(14) AND NOT Dbg_3(0) AND Dbg_3(1) AND
NOT Dbg_3(2) AND NOT Dbg_3(3)));
Seg(3) <= ((N_PZ_279)
OR (N_PZ_256)
OR (CNT(15) AND CNT(14) AND Dbg_4(0) AND Dbg_4(1) AND
Dbg_4(2))
OR (CNT(15) AND NOT CNT(14) AND Dbg_3(0) AND Dbg_3(1) AND
Dbg_3(2))
OR (NOT CNT(15) AND NOT CNT(14) AND Dbg_1(0) AND Dbg_1(1) AND
Dbg_1(2))
OR (CNT(15) AND CNT(14) AND NOT Dbg_4(0) AND Dbg_4(1) AND
NOT Dbg_4(2) AND Dbg_4(3))
OR (CNT(15) AND NOT CNT(14) AND NOT Dbg_3(0) AND Dbg_3(1) AND
NOT Dbg_3(2) AND Dbg_3(3)));
Seg(4) <= ((N_PZ_279)
OR (NOT CNT(15) AND NOT CNT(14) AND Dbg_1(0))
OR (CNT(15) AND CNT(14) AND Dbg_4(0) AND NOT Dbg_4(3))
OR (CNT(15) AND NOT CNT(14) AND Dbg_3(0) AND NOT Dbg_3(3))
OR (CNT(15) AND CNT(14) AND Dbg_4(0) AND NOT Dbg_4(1) AND
NOT Dbg_4(2))
OR (CNT(15) AND NOT CNT(14) AND Dbg_3(0) AND NOT Dbg_3(1) AND
NOT Dbg_3(2)));
Seg(5) <= ((N_PZ_256)
OR (NOT CNT(15) AND NOT CNT(14) AND Dbg_1(1) AND NOT Dbg_1(2))
OR (CNT(15) AND CNT(14) AND Dbg_4(1) AND NOT Dbg_4(2) AND
NOT Dbg_4(3))
OR (CNT(15) AND NOT CNT(14) AND Dbg_3(1) AND NOT Dbg_3(2) AND
NOT Dbg_3(3))
OR (NOT CNT(15) AND NOT CNT(14) AND Dbg_1(0) AND Dbg_1(1) AND
Dbg_1(2))
OR (CNT(15) AND CNT(14) AND Dbg_4(0) AND Dbg_4(1) AND
Dbg_4(2) AND NOT Dbg_4(3))
OR (CNT(15) AND CNT(14) AND Dbg_4(0) AND NOT Dbg_4(1) AND
Dbg_4(2) AND Dbg_4(3))
OR (CNT(15) AND NOT CNT(14) AND Dbg_3(0) AND Dbg_3(1) AND
Dbg_3(2) AND NOT Dbg_3(3))
OR (CNT(15) AND NOT CNT(14) AND Dbg_3(0) AND NOT Dbg_3(1) AND
Dbg_3(2) AND Dbg_3(3)));
Seg(6) <= ((NOT CNT(15) AND CNT(14))
OR (NOT CNT(15) AND NOT Dbg_1(1) AND NOT Dbg_1(2))
OR (NOT CNT(15) AND Dbg_1(0) AND Dbg_1(1) AND Dbg_1(2))
OR (CNT(14) AND NOT Dbg_4(1) AND NOT Dbg_4(2) AND NOT Dbg_4(3))
OR (CNT(15) AND NOT CNT(14) AND NOT Dbg_3(1) AND NOT Dbg_3(2) AND
NOT Dbg_3(3))
OR (CNT(14) AND Dbg_4(0) AND Dbg_4(1) AND Dbg_4(2) AND
NOT Dbg_4(3))
OR (CNT(14) AND NOT Dbg_4(0) AND NOT Dbg_4(1) AND Dbg_4(2) AND
Dbg_4(3))
OR (CNT(15) AND NOT CNT(14) AND Dbg_3(0) AND Dbg_3(1) AND
Dbg_3(2) AND NOT Dbg_3(3))
OR (CNT(15) AND NOT CNT(14) AND NOT Dbg_3(0) AND NOT Dbg_3(1) AND
Dbg_3(2) AND Dbg_3(3)));
WR <= NOT ('0');
Register Legend:
FDCPE (Q,D,C,CLR,PRE,CE);
FDDCPE (Q,D,C,CLR,PRE,CE);
FTCPE (Q,D,C,CLR,PRE,CE);
FTDCPE (Q,D,C,CLR,PRE,CE);
LDCP (Q,D,G,CLR,PRE);
****************************** Device Pin Out *****************************
Device : XC2C256-7-TQ144
Pin Signal Pin Signal
No. Name No. Name
1 VCC 73 VCCIO-1.8
2 KPR 74 KPR
3 KPR 75 KPR
4 KPR 76 KPR
5 KPR 77 KPR
6 KPR 78 KPR
7 KPR 79 KPR
8 VCCAUX 80 KPR
9 KPR 81 KPR
10 KPR 82 KPR
11 KPR 83 KPR
12 KPR 84 VCC
13 RD 85 KPR
14 TXE 86 KPR
15 RXF 87 KPR
16 FIFO_Data<7> 88 KPR
17 FIFO_Data<6> 89 GND
18 FIFO_Data<5> 90 GND
19 KPR 91 KPR
20 KPR 92 KPR
21 KPR 93 VCCIO-1.8
22 KPR 94 STA
23 KPR 95 KPR
24 KPR 96 KPR
25 KPR 97 KPR
26 KPR 98 KPR
27 VCCIO-1.8 99 GND
28 KPR 100 KPR
29 GND 101 KPR
30 KPR 102 KPR
31 KPR 103 KPR
32 KPR 104 KPR
33 KPR 105 FIFO_Data<4>
34 KPR 106 FIFO_Data<2>
35 KPR 107 FIFO_Data<3>
36 GND 108 GND
37 VCC 109 VCCIO-1.8
38 KPR 110 FIFO_Data<0>
39 KPR 111 FIFO_Data<1>
40 KPR 112 KPR
41 KPR 113 KPR
42 KPR 114 KPR
43 KPR 115 KPR
44 WR 116 KPR
45 CLK 117 KPR
46 OE 118 KPR
47 GND 119 KPR
48 KPR 120 KPR
49 KPR 121 KPR
50 KPR 122 TDO
51 KPR 123 GND
52 KPR 124 KPR
53 Seg<1> 125 KPR
54 Seg<5> 126 Dig<0>
55 VCCIO-1.8 127 VCCIO-1.8
56 Seg<0> 128 Dig<1>
57 Seg<4> 129 Dig<2>
58 Seg<3> 130 Dig<3>
59 KPR 131 KPR
60 Seg<2> 132 KPR
61 Seg<6> 133 KPR
62 GND 134 KPR
63 TDI 135 KPR
64 LEDs<3> 136 KPR
65 TMS 137 KPR
66 LEDs<2> 138 KPR
67 TCK 139 KPR
68 LEDs<1> 140 KPR
69 LEDs<0> 141 VCCIO-1.8
70 KPR 142 KPR
71 KPR 143 RST
72 GND 144 GND
Legend : NC = Not Connected, unbonded pin
PGND = Unused I/O configured as additional Ground pin
KPR = Unused I/O with weak keeper (leave unconnected)
WPU = Unused I/O with weak pull up (leave unconnected)
TIE = Unused I/O floating -- must tie to VCC, GND or other signal
VCC = Dedicated Power Pin
VCCAUX = Power supply for JTAG pins
VCCIO-3.3 = I/O supply voltage for LVTTL, LVCMOS33, SSTL3_I
VCCIO-2.5 = I/O supply voltage for LVCMOS25, SSTL2_I
VCCIO-1.8 = I/O supply voltage for LVCMOS18
VCCIO-1.5 = I/O supply voltage for LVCMOS15, HSTL_I
VREF = Reference voltage for indicated input standard
*VREF = Reference voltage pin selected by software
GND = Dedicated Ground Pin
TDI = Test Data In, JTAG pin
TDO = Test Data Out, JTAG pin
TCK = Test Clock, JTAG pin
TMS = Test Mode Select, JTAG pin
PROHIBITED = User reserved pin
**************************** Compiler Options ****************************
Following is a list of all global compiler options used by the fitter run.
Device(s) Specified : xc2c256-7-TQ144
Optimization Method : DENSITY
Multi-Level Logic Optimization : ON
Ignore Timing Specifications : OFF
Default Register Power Up Value : LOW
Keep User Location Constraints : ON
What-You-See-Is-What-You-Get : OFF
Exhaustive Fitting : OFF
Keep Unused Inputs : OFF
Slew Rate : FAST
Set Unused I/O Pin Termination : KEEPER
Global Clock Optimization : ON
Global Set/Reset Optimization : ON
Global Ouput Enable Optimization : ON
Enable Input Registers : ON
Function Block Fan-in Limit : 38
Use DATA_GATE Attribute : ON
Set Tristate Outputs to Termination Mode : KEEPER
Default Voltage Standard for All Outputs : LVCMOS18
Input Limit : 32
Pterm Limit : 28