Xmega Application Note


ebi_sdram_example.c

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00001 /* This file has been prepared for Doxygen automatic documentation generation.*/
00051 #include "avr_compiler.h"
00052 #include "ebi_driver.h"
00053 
00055 #define SDRAM_ADDR 0x4000
00056 
00058 #define SDRAM(addr) ((uint8_t *) SDRAM_ADDR)[addr]
00059 
00061 #define VECTOR_SIZE 1000
00062 
00063 
00064 
00088 int main( void )
00089 {
00090         /* Flag indicating correct data transfer to and from SDRAM */
00091         bool equal = true;
00092 
00093         /* Set signals which are active-low to high value */
00094         PORTH.OUT = 0x0F;
00095 
00096         /* Configure bus pins as outputs(except for data lines). */
00097         PORTH.DIR = 0xFF;
00098         PORTK.DIR = 0xFF;
00099         PORTJ.DIR = 0xF0;
00100 
00101         /* Set direction and output value of Chip Select line (C0). */
00102         PORTC.DIR = 0x01;
00103         PORTC.OUT = 0x00;
00104 
00105         /* Initialize EBI. */
00106         EBI_Enable( EBI_SDDATAW_4BIT_gc,
00107                     EBI_LPCMODE_ALE1_gc,
00108                     EBI_SRMODE_ALE12_gc,
00109                     EBI_IFMODE_3PORT_gc );
00110 
00111         /* Initialize SDRAM */
00112         EBI_EnableSDRAM( EBI_CS_ASPACE_8KB_gc,   /* 8 KB address space. */
00113                          (void *) SDRAM_ADDR,    /* Base address. */
00114                          false,                  /* 2 cycle CAS Latency. */
00115                          false,                  /* 11 Row bits. */
00116                          EBI_SDCOL_8BIT_gc,      /* 8 Column bits. */
00117                          EBI_MRDLY_1CLK_gc,      /* 1 cycle Mode Register Delay. */
00118                          EBI_ROWCYCDLY_1CLK_gc,  /* 1 cycle Row Cycle Delay. */
00119                          EBI_RPDLY_1CLK_gc,      /* 1 cycle Row to Pre-charge Delay. */
00120                          EBI_WRDLY_1CLK_gc,      /* 1 cycle Write Recovery Delay. */
00121                          EBI_ESRDLY_1CLK_gc,     /* 1 cycle Exit Self Refresh to Active Delay. */
00122                          EBI_ROWCOLDLY_1CLK_gc,  /* 1 cycle Row to Column Delay. */
00123                          0x03FF,                 /* 1023 cycle Refresh Period (32.8 ms @ 2MHz). */
00124                          0x0100 );               /* 256 cycle Initialization Delay (128 us @ 2MHz). */
00125 
00126         /* Fill SDRAM with data. */
00127         for (uint16_t i = 0; i < VECTOR_SIZE; i++) {
00128                 SDRAM(i) =  (uint8_t) i & 0xFF;
00129         }
00130 
00131         /* Read back from SDRAM and verify */
00132         for (uint16_t i = 0; i < VECTOR_SIZE; i++) {
00133                 if (SDRAM(i) != ((uint8_t) i & 0xFF)){
00134                         equal = false;
00135                         break;
00136                 }
00137         }
00138 
00139         /* Report success or failure. */
00140 
00141         if (equal) {
00142                 while(true) {
00143                 /* Breakpoint for success. */
00144                         nop();
00145                 }
00146         }
00147         else {
00148                 while(true) {
00149                 /* Breakpoint for failure. */
00150                         nop();
00151                 }
00152         }
00153 }
@DOC_TITLE@
Generated on Wed Apr 23 08:16:46 2008 for AVR1312 Using the XMEGA External Bus Interface by doxygen 1.5.5