Xmega Application Note | |||||
This file contains an example application that demonstrates the EBI driver. It shows how to configure the EBI for 3-port SDRAM operation. The example fills a data pattern in the memory, copies back and compares the copied block.
Copyright (c) 2008, Atmel Corporation All rights reserved.
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Definition in file ebi_sdram_example.c.
#include "avr_compiler.h"
#include "ebi_driver.h"
Go to the source code of this file.
Defines | |
#define | SDRAM(addr) ((uint8_t *) SDRAM_ADDR)[addr] |
Macro to access SDRAM. | |
#define | SDRAM_ADDR 0x4000 |
Address where we want SDRAM to be accessed. | |
#define | VECTOR_SIZE 1000 |
Number of test bytes to store to SDRAM. | |
Functions | |
int | main (void) |
Test function for EBI with SDRAM. |
#define SDRAM | ( | addr | ) | ((uint8_t *) SDRAM_ADDR)[addr] |
#define SDRAM_ADDR 0x4000 |
Address where we want SDRAM to be accessed.
Definition at line 55 of file ebi_sdram_example.c.
Referenced by main().
#define VECTOR_SIZE 1000 |
Number of test bytes to store to SDRAM.
Definition at line 61 of file ebi_sdram_example.c.
Referenced by main().
int main | ( | void | ) |
Test function for EBI with SDRAM.
Hardware setup for 3-port SDRAM interface:
PORTK[7:0] - A[7:0]
PORTJ[7:0] - {A[11:8],D[3:0]}
PORTH[7:0] - {WE,CAS,RAS,DQM,BA0,BA1,CKE,CLK}
Since the EBI in 3-port mode does not have any spare pins for Chip Select, this shoul be controlled by a General Purpose IO pin (PIN C0 in this example). A pull-up resistor should be connected to this pin to ensure that the Chip Select is kept high during start-up.
The EBI SDRAM settings need to be set according to the characteristics of the SDRAM in use. The settings for used with the SDRAM in this example is commented in the EBI_EnableSDRAM function call.
The setup is tested by writing a set of data to the SDRAM. The data is then read back and verified. At the end, the program will be stuck in one of two infinite loops, dependent on whether the test passed or not.
Definition at line 88 of file ebi_sdram_example.c.
References EBI_Enable(), EBI_EnableSDRAM(), SDRAM, SDRAM_ADDR, and VECTOR_SIZE.
00089 { 00090 /* Flag indicating correct data transfer to and from SDRAM */ 00091 bool equal = true; 00092 00093 /* Set signals which are active-low to high value */ 00094 PORTH.OUT = 0x0F; 00095 00096 /* Configure bus pins as outputs(except for data lines). */ 00097 PORTH.DIR = 0xFF; 00098 PORTK.DIR = 0xFF; 00099 PORTJ.DIR = 0xF0; 00100 00101 /* Set direction and output value of Chip Select line (C0). */ 00102 PORTC.DIR = 0x01; 00103 PORTC.OUT = 0x00; 00104 00105 /* Initialize EBI. */ 00106 EBI_Enable( EBI_SDDATAW_4BIT_gc, 00107 EBI_LPCMODE_ALE1_gc, 00108 EBI_SRMODE_ALE12_gc, 00109 EBI_IFMODE_3PORT_gc ); 00110 00111 /* Initialize SDRAM */ 00112 EBI_EnableSDRAM( EBI_CS_ASPACE_8KB_gc, /* 8 KB address space. */ 00113 (void *) SDRAM_ADDR, /* Base address. */ 00114 false, /* 2 cycle CAS Latency. */ 00115 false, /* 11 Row bits. */ 00116 EBI_SDCOL_8BIT_gc, /* 8 Column bits. */ 00117 EBI_MRDLY_1CLK_gc, /* 1 cycle Mode Register Delay. */ 00118 EBI_ROWCYCDLY_1CLK_gc, /* 1 cycle Row Cycle Delay. */ 00119 EBI_RPDLY_1CLK_gc, /* 1 cycle Row to Pre-charge Delay. */ 00120 EBI_WRDLY_1CLK_gc, /* 1 cycle Write Recovery Delay. */ 00121 EBI_ESRDLY_1CLK_gc, /* 1 cycle Exit Self Refresh to Active Delay. */ 00122 EBI_ROWCOLDLY_1CLK_gc, /* 1 cycle Row to Column Delay. */ 00123 0x03FF, /* 1023 cycle Refresh Period (32.8 ms @ 2MHz). */ 00124 0x0100 ); /* 256 cycle Initialization Delay (128 us @ 2MHz). */ 00125 00126 /* Fill SDRAM with data. */ 00127 for (uint16_t i = 0; i < VECTOR_SIZE; i++) { 00128 SDRAM(i) = (uint8_t) i & 0xFF; 00129 } 00130 00131 /* Read back from SDRAM and verify */ 00132 for (uint16_t i = 0; i < VECTOR_SIZE; i++) { 00133 if (SDRAM(i) != ((uint8_t) i & 0xFF)){ 00134 equal = false; 00135 break; 00136 } 00137 } 00138 00139 /* Report success or failure. */ 00140 00141 if (equal) { 00142 while(true) { 00143 /* Breakpoint for success. */ 00144 nop(); 00145 } 00146 } 00147 else { 00148 while(true) { 00149 /* Breakpoint for failure. */ 00150 nop(); 00151 } 00152 } 00153 }
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