Overview

AVR Simulator Overview

Notice: Starting with AVR Studio 4.14, AVR Simulator 2 is the official simulator for most new AVR devices. In particular, the new ATxmega family is only suppported by Simulaotor 2. In the transition period, quite a few other devices are supported by both versions. However, we recommend using Simulator 2 whenever possible.

The AVR Simulator is a software simulator for the AVR architecture and devices. It simulates the CPU, including all instructions, interrupts and most of the on-chip I/O modules. See Simulator Modules for information about which features are supported.

The AVR Simulator operates within the AVR Studio application as a debug target. This enables the user to use the normal debug commands such as Run, Break, Reset, Single step, set breakpoints and watch variables. The I/O, memory and register views are fully functional using the AVR Simulator.

Note that the I/O view, memory and registers windows are not updated while the Simulator is running. Neither can the contents of these windows be modified in run mode.

For an overview of what's new in this release, see the Change History.

See also

Known Issues

Simulator O ptions

Simulator 2


Simulator V2

AVR Simulator 2

Introduction

Simulator 2 is a new simulator based on software models derived directly from the hardware designs, unlike the old simulator that is based on hand-written code. This results in significantly more accurate and complete simulation of digital peripherals than the old simulator. Starting with AVR Studio 4.14, Simulator 2 is the primary simulator for AVR Studio, and most new devices will only be supported in Simulator 2.

Status

As of AVR Studio 4.15, there are still some major features missing in Simulator2 compared to the old simulator. These include:

  • Data breakpoints (#7502)

  • External RAM support (#7570)

See also known issues section below.

We do however encourage its use if working with one of the supported devices. Digital peripherals like timers, watchdog, etc generally work much better than in the old simulator.

Supported devices

  • ATtiny10

  • ATtiny9
  • ATtiny5
  • ATtiny4

  • ATtiny13/ATtiny13A

  • ATtiny20

  • ATtiny2313A/4313

  • ATtiny25/45/85

  • ATtiny261/461/861

  • ATtiny40

  • ATtiny43U

  • ATtiny48/ATtiny88

  • ATmega128/ATmega128A

  • ATmega1284P/644P

  • ATmega164P/164PA/324P/324PA

  • ATmega165/165P

  • ATmega169/169P

  • ATmega325/325P/3250/3250P

  • ATmega329/329P/3290/3290P

  • ATmega645/6450

  • ATmega649/6490

  • ATmega48A/48P/88A/88P/88PA/168A/168P/168PA/328P

  • ATmega8/16HVA
  • ATmega16HVA2

  • ATmega32HVB/16HVB

  • ATmega64HVE/32HVE

  • ATXMEGA128A1/ATXMEGA64A1

  • ATXMEGA256A3

  • ATXMEGA256A3B/ATXMEGA256A3BU

  • ATXMEGA192A3/ATXMEGA128A3/ATXMEGA64A3

  • ATXMEGA256D3/192D3/128D3/64D3

  • ATXMEGA32A4/16A4

  • ATXMEGA32D4/16D4

  • ATtiny24(A)/ATtiny44(A)/ATtiny84(A)

  • ATtiny26

  • ATtiny1634

  • ATmega8(A)

  • ATmega32(A)/ATmega16(A)

  • ATmega64(A)

  • ATmega2560/2561

  • ATmega1280/1281

  • ATmega640

  • ATXMEGA256A3U/ATXMEGA192A3U/ATXMEGA128A3U/ATXMEGA64A3U

  • ATXMEGA32A4U/ATXMEGA16A4U

Support for more devices will be introduced as part of regular AVR Studio releases and service packs, or as standalone part-support packs. Simulator2 also to a greater extent allows simulation of the effect of fuses, lockbits, etc which can be set in the new Simulator 2 Options dialog.

Beware that the default fuse settings generally match the real device, which can cause surprises. (Exception: The ATmega128 mega103 compatibility fuse (M103C) is not programmed by default). Examples:

  • In most tiny devices, the SELFPRGEN fuse is unprogrammed by default, preventing SPM from working. Set this fuse when working with SPM.

  • Many tiny devices have external reset as an alternative port function, and a RSTDISBL fuse to disable the external reset pin. When unprogrammed (the default setting), the corresponding port pin will not work as expected. Beware that setting this fuse disables External Reset for the AVR Studio button, select Power-On Reset wjen setting RSTDISBL. (#8244)..

Consult the device data sheet for info about fuses and their default settings.

See also: Experimental stimuli feature in AVR Studio 4.16, see AVR Simulator2 Stimuli section.

Known issues in 4.18 SP1

  • ATmega16HVA2 has a HVA compatibility fuse (COMPMODE), this is used by the simulator to provide HVA support. To avoid confusion, it is recommended to select a HVA device in the device dialog rather than explicitly setting this fuse in the Simulator Options when the HVA2 in compatibility mode is to be simulated.
  • ATtiny40 RAMDR register cannot be written from AVR Studio's I/O view. Workaround: write SRAM directly via memory view.
  • ATmega16HVB stack pointer does not intialize correctly and must be initialized by application. This is an issue with the actual chip and the simulator just reflects reality.
  • ATmega169PA/165PA/329P/325P/3250P/3290P/649P/645P/6490P/6450P watchdog reset does not work (#9301)

  • Entering sleep mode hangs AVR Studio (#9365) still an issue with ATxmegaA1/A3/D3 devices

  • PRR register of ATtiny25/45/85 does not work (#5584, it works with the other devices having PRR).

  • ATtiny25/45/85: Watchdog timeout too long (~64 times longer than it should be @1MHz)

  • System clock prescaler not included in simulator models, writing CLKPR will not affect system clock. (all devices except ATxmega and AVR8L based devices)

  • Writing/erasing FLASH (SPM) and EEPROM from software not yet implemented in ATxmega devices (#7611)

  • Simulation of ATxmega devices is slow compared to other devices.

  • The option Stop on BREAK instruction in the Simulator 2 Options dialog is not saved in the project file, and must be re-enabled in every session.

  • All changes made in the Simulator 2 Options dialog causes the simulated device to be reset when OK is pressed.

  • It is possible to disable the reset button entirely by means of setting the RSTDISBL fuse when External Reset is selected for the Reset button, or selecting BOD reset when BOD is disabled. It is recommended to keep Power-On Reset for the reset button when playing with fuse settings. (#8244)

  • When writing to I/O PORT registers and the port is configured as output, the change will show up immediately in the PIN register, not one cycle delayed as on the real chip (#7188). This only affects the AVR Studio I/O view, not the execution of programs.

Changelog

AVR Studio 4.18 SP1

  • Added support for ATmega16HVA2.

  • Added support for ATmega16HVA/8HVA (using HVA2 model and compatibility fuse)

  • Fixed: Set next statement executed instruction after cursor before jumping to the new statement (#10806)
  • Fixed: When a new device was selected using Select Platform and Device, the fuse settings from the old device were copied into the new device. Now the new device starts with its default fuse settings. (#10941)

AVR Studio 4.18

  • Added support for ATxmegaA4, ATxmegaD4, ATtiny20, ATtiny40, ATtiny4, ATtiny5, ATtiny9, ATtiny2313A/4313, ATmega32HVB/16HVB, ATmega64HVE/32HVE.

  • ATtiny10 VLMCSR bit fixed (#9367)

AVR Studio 4.16

  • NEW! Added experimental stimuli feature, see AVR Simulator2 Stimuli section.

  • Fixed: Entering sleep mode hangs AVR Studio (#9365) for all devices except ATxmegaA1/A3/D3.

  • Fixed: I/O view write to read-only regster did not work and could cause crash (#9242)

  • Fixed: LDD instruction did not work against certain I/O registers (#9284)

  • Fixed: Wrong initialisation of PIN registers in mega169/165/329[0]/325[0]/649[0]/649[0] devices (#9296)

AVR Studio 4.15

  • Simulator2 should now work with Windows 98 and NT4 (#6413)

  • Default Reset button action changed from External Reset to Power-On Reset. (#8244)

  • AES problem in xmega simulator fixed (#8102)

  • Fixed: When writing to I/O PORT registers and the port is configured as output, change is shown one cycle in PIN register (#7188)

  • Corrected initial value of PCMSK register in ATtiny25/45/85 (#7881)

  • Fixed: xmega128A1 PLL never ready when enabled (#7921)

  • Fixed: Write TWHS bit in TWHSR register in tiny48/88 not working (#8037)

  • Added support for ATxmega256A3(B), ATxmega128A3, ATxmega64A3, ATtiny10, ATtiny261/461/861, ATmega32HVB, ATmega169[P}, ATmega165[P],. ATmeg325[P], ATmega3250[P], ATmega329[P], ATmega3290[P], ATmega645, ATmega6450, ATmega649, ATmega6490, and some A-suffix mega devices.

AVR Studio 4.14 SP1

  • Added support for ATtiny13/ATtiny13A.

AVR Studio 4.14 RELEASE

  • Fixed xmega power reduction registers PRPA-PRPF in I/O view (#7760)

AVR Studio 4.14 RC1

  • Added option to stop simulator if executing a BREAK instruction (#7550)

  • Fixed: ATmega128 and ATtiny25/45/85 have additional MCUSR reset flags issues (#7431)

  • Fixed: If the user issues a manual Break of Run To Cursor, Step Out, or Step Over operations, the debugger will not stop at a valid source statement (#7434).

AVR Studio 4.14-Beta2

  • Support for ATtiny88 added.

  • Fixed #7381: If Run To Cursor, Step Out, and Step Over didn't reach their stop criterion, AVR Studio was sometimes left in an unresponsive state.

AVR Studio 4.14-Beta1

  • New Simulator 2 Options dialog allows setting fuses/lockbits, etc.

  • Debugger break from Run mode now works properly

  • Hit count property in program breakpoints implemented

  • Step over and Step Out implemented

  • Numerous bugs fixed

  • Added support for ATxmega128A1(Rev.D)

AVR Studio 4.13 SP2

  • Added support for quite a few new devices.


Simulator Options

The Simulator Options dialog is available while the debug session is active. To bring up the dialog, select the Debug menu and choose AVR Simulator Options.

The Simulator Options dialog have two panes, Device selection and Stimuli and logging.


Device selection

In the Device selection pane (see figure below), the following options can be selected:

Device

The device that is being simulated. Information about the device is shown in the window to the right. Choosing another device will cause the AVR Simulator to reconfigure for the new device and reload the project.

Frequency

Specifies the speed of the device being simulated. This setting has no effect on the simulation, it is only used for the calculation of the stop watch value in the I/O View.

Boot loader

If the Enable Boot reset checkbox is set, the device will start from the boot reset address when it is reset.

The boot reset address is determined by the the boot reset listbox, which contains all valid boot reset addresses for the selected device. This address also determines the Interrupt Vector start address when the Interrupt Vector Select (IVSEL) bit is set.

Not all devices support boot loaders.

Enable external Memory

If the Enable external Memory checkbox is set, external SRAM will be simulated and available to the application being run.

If the selected device does not support external SRAM, this option will be disabled.


Stimuli and logging

In the Stimuli and logging pane, stimuli and logging on the device's ports can be specified.

Stimulating Ports

An I/O port can take its input from a stimuli file by specifying the port in the Port listbox and clicking the Stimuli button. Then enter the stimuli file name in the File field, or click the browse ( [image]) button. Finally, click the Add Entry button. The new stimuli file will then appear in the Action list. To remove the stimuli file, select it in the list and click the Delete Entry button.

The stimuli value will appear in the PIN register one cycle after the cycle number specified in the stimuli file.

The stimuli file format is described here.

Logging Port Values

The values of the I/O ports can be logged to a file by specifying the port in the Port listbox and clicking the Logging button. Then enter the log file in the File field, or click the browse ( [image]) button. Finally, click the Add Entry button. The new log file will then appear in the Action list. To remove the log file, select it in the list and click the Delete Entry button.

By selecting the To screen checkbox, the port values will be logged to the AVR Studio Messages window in addition to the file.

Each time the value of the PORT register changes, the new value will be logged. The value can be set either by the program or by the user modifying the register in the I/O view, watch window or memory window.

The log file format is described here.


Stimuli and Log File Format

The stimuli file specifies values to be applied to the PIN register of an I/O port at certain times. The log file describes changes to the PORT register of an I/O port.

Stimuli and log files use the same format. A stimuli/log file consists of multiple lines of colon-separated cycle number/value pairs. For instance, the following stimuli file causes the values 00, AB, AC to be set at cycles 0, 9 and 14, respectably.

000000000:00

000000009:AB

000000014:AC

999999999:FF

Cycle numbers are decimal value, while values are hexadecimal. The cycle number can be from 1 to 9 digits. The value must be between 0 and FF.

The last line must be

999999999:FF

See also

Stimuli and Logging options


Simulator Modules

This section contains a brief overview of the various I/O modules that exist in AVR devices, and the status of their support in the AVR Simulator.

See also Known Issues

I/O Ports

I/O ports are simulated as on the real device. This includes the 1.5 clock cycle debouncing delay found in the standard port logic hardware in actual AVR parts. When an I/O module take control over a pin, the value read from the PINx register is the value generated by that I/O module. There are known issues for I/O Ports.

External Interrupts and Pin Change Interrupts

All external and pin change interrupts are supported by the simulator.

Timer/Counters

Timer/Counters are simulated correctly except where noted in the Known Issues section.

Output Compare Modulators are not supported.

UART and USART

There are known issues with UART/USARTs on all devices.

Serial Peripheral Interface (SPI)

SPI is supported, except as noted in the known issues section.

Universal Serial Interface (USI)

USI is not supported.

Two-wire Serial Interface (TWI)

TWI is not supported.

Analog Comparator (AC)

Analog Comparator is not supported.

Analog to Digital Converter (ADC)

Analog input is not supported. However, based on the ADC Prescaler Select bits (ADPS), the ADIF flag is set after the correct number of cycles. The ADC completion interrupt is also simulated correctly.

The ADC Data register (ADCH/ADCL) can be manually set e.g in the I/O view.

LCD Controller

The LCD Controller is supported on all parts with an LCD Controller.

Watchdog

The watchdog is support on some parts. See Known Issues for details.


Known Issues

Known Issues in AVR Simulator 1

The Known Issues list is organized in two major sections; the first describes general simulator issues, while the second describes device specific issues.

If your device is supported by AVR Simulator 2, we recommend using that to avoid the issues listed below.

ATxmega devices are ONLY supported by AVR Simulator 2.

General Simulator Issues

The issues in this section apply to all AVR devices.

Unsupported modules

Simulation of TWI, USI and analog peripheral is not yet implemented. All instructions, interrupts and other peripherals are supported. See the Simulator Modules for more information.

Register behaviour

Some simulator modules do not properly simulate the register buffering and write order requirement of register pairs such as TCNT1H/TCNT1L. The value of the high byte register is immediately set when written to.

Some register bits that should be cleared by setting them (writing 1) will be cleared if they are written to 0.

External SRAM

To use external RAM in the simulator, the project must be reopened after setting the option in the Device selection dialog page.

Read-While-Write Self-Programming

Read-While-Write Self-Programming can be done from anywhere in the Flash program memory. Neither is the border between Read-While-Write and No-Read-While-Write sections respected.

Sleep Modes

The simulator only supports the Idle sleep mode.

Watchdog

The Watchdog is not supported on all devices. See Device specific issues.

When a watchdog reset occurs, the program will not always stop at breakpoints on the reset vector.

The watchdog timer assumes a clock speed of 1MHz, timing will not be correct at other clock settings.

I/O Ports

PIN registers can be written to, and the value will stay in the PIN register.

Ports that have less than eight bits are not properly masked. All eight bits can be used in the simulator.

Timer/Counters

16-bit Timer/Counters on all devices have several problems with PWM, prescaler and output compare. Output compare registers are not buffered properly.

The Asynchronous Status Register (ASSR) is not supported in timers with asynchronous mode. This is due to lack of a generic external clock implementation.

UART/USART

The UART/USART UDR register can only be modified from the application. Input via stimuli files or by modifying the I/O view etc is not possible.

Terminal I/O window is not implemented. This feature is available in AVR Studio 3.xx.

When writing to UCSRC, the value will be copied to UBRRH unless bit 7 is also set in in the same write operation. This behaviour is erroneous on devices that have separate locations for these registers. Another workaround is to write UBRRH after UCSRC.

Serial Peripheral Interface (SPI)

The double speed mode (SPI2X) is not supported in any devices.

Power Reduction Register (PRR)

For devices having Power Reduction Register, shutdown of peripheral modules controlled by the PRR is not simulated; the peripherals will continue to operate normally.

Device specific issues

The following devices have known issues specific to the device.

AT86RF401 AT90CAN32/64/128 AT90PWM2/3/216/316 AT90S1200 AT90S2313 AT90S2323 AT90S2343 AT90S4414 AT90S4433 AT90S4434 AT90S8515 AT90S8535 | ATmega103 ATmega128 ATmega16 ATmega161 ATmega162 ATmega163 ATmega165/165P ATmega169/169P ATmega2560/2561 ATmega32 ATmega323 ATmega325/325P ATmega3255/3250P | ATmega329/329P ATmega3290/3290P ATmega406 ATmega48P/88P/168P/328P ATmega64 ATmega640/1280/1281 ATmega164P/324P/644/644P ATmega645 ATmega6450 ATmega649 ATmega6490 ATmega8 ATmega16HVA | ATmega8515 ATmega8535 ATtiny11 ATtiny13 ATtiny15 ATtiny22 ATtiny24 ATtiny26 ATtiny261/461/861 ATtiny28 ATtiny25/45/85 ATtiny2313 ATtiny43u
 |  | ATmega32C1/M1 | ATtiny48
 |  | ATmega32U4 | ATtiny167


Notes for AT86RF401

No I/O modules are simulated for the AT86RF401.


Notes for AT90CAN32/64/128

The CAN I/O module is implemented as an AVR Studio plugin. If this plugin is not installed, AVR Simulator will print an error message "CAN (AVRSimIOCAN00.SimIOCAN00) not supported." This plugin can be downloaded from Atmel's website at http://www.atmel.com/products/avr/.

When writing to UCSRnC, the value will be copied to UBRRnH unless bit 7 is set. This behaviour should not happen on devices that have separate locations for these registers. A workaround is to write UBRRnH after UCSRnC.

The JTD bit in the MCUCR register must be set to the desired value twice within four cycles to change its value. In the simulator the JTD bit can be written directly.

The ADC noise reduction function is not supported. Setting the ADIF flag will not wake the CPU from sleep mode.


Notes for AT90PWM2/3/216/316

The Analog Comparators, Power Stage Controllers and the DAC are not simulated.

When writing to UCSRC, the value will be copied to UBRRH unless bit 7 is set. This behaviour should not happen on devices that have separate locations for these registers. A workaround is to write UBRRH after UCSRC.

The ADC noise reduction function is not supported. Setting the ADIF flag will not wake the CPU from sleep mode.


Notes for AT90S1200

The Watchdog is not simulated.


Notes for AT90S2313

The Watchdog is not simulated.


Notes for AT90S2323

The Watchdog is not simulated.


Notes for AT90S2343

The Watchdog is not simulated.


Notes for AT90S4414

The Watchdog is not simulated.


Notes for AT90S4433

The Watchdog is not simulated.

The ADC noise reduction function is not supported. Setting the ADIF flag will not wake the CPU from sleep mode.


Notes for AT90S4434

The Watchdog is not simulated.


Notes for AT90S8515

The Watchdog is not simulated.


Notes for AT90S8535

The ADC noise reduction function is not supported. Setting the ADIF flag will not wake the CPU from sleep mode.

The Watchdog is not simulated.


Notes for ATmega103

The Watchdog is not simulated.


Notes for ATmega128

This device is supported by AVR Simulator 2, and we recommend using that to avoid the issues listed below.

When writing to UCSRnC, the value will be copied to UBRRnH unless bit 7 is set. This behaviour should not happen on devices that have separate locations for these registers. A workaround is to write UBRRnH after UCSRnC.

The JTD bit in the MCUCSR register must be set to the desired value twice within four cycles to change its value. In the simulator the JTD bit can be written directly.

The ADC noise reduction function is not supported. Setting the ADIF flag will not wake the CPU from sleep mode.


Notes for ATmega16

The USART's UBRRH and UCSRC registers share the same I/O address. Writing to one of the registers will cause both registers to contain the new value, regardless of the value of URSEL. Reading these registers do not work as described in the datasheet.

The JTD bit in the MCUCSR register must be set to the desired value twice within four cycles to change its value. In the simulator the JTD bit can be written directly.

The ADC noise reduction function is not supported. Setting the ADIF flag will not wake the CPU from sleep mode.


Notes for ATmega161

The Watchdog is not simulated.


Notes for ATmega162

USART0 and USART1's UBRRnH and UCSRnC registers share the same I/O address. Writing to one of the registers will cause both registers to contain the new value, regardless of the value of URSEL. Reading these registers do not work as described in the datasheet.

The JTD bit in the MCUCSR register must be set to the desired value twice within four cycles to change its value. In the simulator the JTD bit can be written directly.


Notes for ATmega163

The Watchdog is not simulated.


Notes for ATmega2560/2561

When writing to UCSRnC, the value will be copied to UBRRnH unless UMSELn1 is set. This behaviour should not happen on devices that have separate locations for these registers. A workaround is to write UBRRnH after UCSRnC.

The JTD bit in the MCUCR register must be set to the desired value twice within four cycles to change its value. In the simulator the JTD bit can be written directly.

The ADC noise reduction function is not supported. Setting the ADIF flag will not wake the CPU from sleep mode.

Timer/Counter2

  • Output compare pins and FOC does not work.

  • Prescaler reset does not work correctly.

  • OCR2A/B registers are not buffered correctly in PWM mode.


Notes for ATmega164/324/644

Notes for ATmega164P/324P/644/644P/1284P

These devices are supported by AVR Simulator 2, and we recommend using that to avoid the issues listed below.

When writing to UCSRnC, the value will be copied to UBRRnH unless UMSELn1 is set. This behaviour should not happen on devices that have separate locations for these registers. A workaround is to write UBRRnH after UCSRnC.

The JTD bit in the MCUCR register must be set to the desired value twice within four cycles to change its value. In the simulator the JTD bit can be written directly.

The ADC noise reduction function is not supported. Setting the ADIF flag will not wake the CPU from sleep mode.

Timer/Counter2

  • Output compare pins and FOC does not work.

  • Prescaler reset does not work correctly.

  • OCR2A/B registers are not buffered correctly in PWM mode.


Notes for ATmega165

Notes for ATmega165/165P

When writing to UCSRC, the value will be copied to UBRRH unless bit 7 is set. This behaviour should not happen on devices that have separate locations for these registers. A workaround is to write UBRRH after UCSRC.

The JTD bit in the MCUCR register must be set to the desired value twice within four cycles to change its value. In the simulator the JTD bit can be written directly.

The ADC noise reduction function is not supported. Setting the ADIF flag will not wake the CPU from sleep mode.

The Watchdog is not simulated.


Notes for ATmega169

Notes for ATmega169/169P

When writing to UCSRC, the value will be copied to UBRRH unless bit 7 is set. This behaviour should not happen on devices that have separate locations for these registers. A workaround is to write UBRRH after UCSRC.

The JTD bit in the MCUCR register must be set to the desired value twice within four cycles to change its value. In the simulator the JTD bit can be written directly.

The ADC noise reduction function is not supported. Setting the ADIF flag will not wake the CPU from sleep mode.

The Watchdog is not simulated.


Notes for ATmega32

The USART's UBRRH and UCSRC registers share the same I/O address. Writing to one of the registers will cause both registers to contain the new value, regardless of the value of URSEL. Reading these registers do not work as described in the datasheet.

The JTD bit in the MCUCSR register must be set to the desired value twice within four cycles to change its value. In the simulator the JTD bit can be written directly.


Notes for ATmega323

The USART's UBRRH and UCSRC registers share the same I/O address. Writing to one of the registers will cause both registers to contain the new value, regardless of the value of URSEL. Reading these registers do not work as described in the datasheet.

The Watchdog is not simulated.


Notes for ATmega325

Notes for ATmega325/325P

When writing to UCSR0C, the value will be copied to UBRR0H unless bit 7 is set. This behaviour should not happen on devices that have separate locations for these registers. A workaround is to write UBRR0H after UCSR0C.

The JTD bit in the MCUCR register must be set to the desired value twice within four cycles to change its value. In the simulator the JTD bit can be written directly.

The ADC noise reduction function is not supported. Setting the ADIF flag will not wake the CPU from sleep mode.

The Watchdog is not simulated.


Notes for ATmega3250

Notes for ATmega3250/3250P

When writing to UCSR0C, the value will be copied to UBRR0H unless bit 7 is set. This behaviour should not happen on devices that have separate locations for these registers. A workaround is to write UBRR0H after UCSR0C.

The JTD bit in the MCUCR register must be set to the desired value twice within four cycles to change its value. In the simulator the JTD bit can be written directly.

The ADC noise reduction function is not supported. Setting the ADIF flag will not wake the CPU from sleep mode.

The Watchdog is not simulated.


Notes for ATmega329

Notes for ATmega329/329P

When writing to UCSR0C, the value will be copied to UBRR0H unless bit 7 is set. This behaviour should not happen on devices that have separate locations for these registers. A workaround is to write UBRR0H after UCSR0C.

The JTD bit in the MCUCR register must be set to the desired value twice within four cycles to change its value. In the simulator the JTD bit can be written directly.

The ADC noise reduction function is not supported. Setting the ADIF flag will not wake the CPU from sleep mode.

The Watchdog is not simulated.


Notes for ATmega3290

Notes for ATmega3290/3290P

When writing to UCSR0C, the value will be copied to UBRR0H unless bit 7 is set. This behaviour should not happen on devices that have separate locations for these registers. A workaround is to write UBRR0H after UCSR0C.

The JTD bit in the MCUCR register must be set to the desired value twice within four cycles to change its value. In the simulator the JTD bit can be written directly.

The ADC noise reduction function is not supported. Setting the ADIF flag will not wake the CPU from sleep mode.

The Watchdog is not simulated.


Notes for ATmega406

Timer/Counter1 is not supported.

The special features such as the Coulomb counter, V-ADC, Voltage Reference and Temperature Sensor, Battery Protection, FET Control and Cell Balancing are not simulated.

The JTD bit in the MCUCR register must be set to the desired value twice within four cycles to change its value. In the simulator the JTD bit can be written directly.


Notes for ATmega48P/88P/168P/328P

These devices are supported by AVR Simulator 2, and we recommend using that to avoid the issues listed below.

When writing to UCSR0C, the value will be copied to UBRR0H unless UMSEL01 is set. This behaviour should not happen on devices that have separate locations for these registers. A workaround is to write UBRR0H after UCSR0C.

The ADC noise reduction function is not supported. Setting the ADIF flag will not wake the CPU from sleep mode.

Timer/Counter2

  • Output compare pins and FOC does not work.

  • Prescaler reset does not work correctly.

  • OCR2A/B registers are not buffered correctly in PWM mode.


Notes for ATmega64

When writing to UCSRnC, the value will be copied to UBRRnH unless bit 7 is set. This behaviour should not happen on devices that have separate locations for these registers. A workaround is to write UBRRnH after UCSRnC.

The JTD bit in the MCUCSR register must be set to the desired value twice within four cycles to change its value. In the simulator the JTD bit can be written directly.

The ADC noise reduction function is not supported. Setting the ADIF flag will not wake the CPU from sleep mode.


Notes for ATmega640/1280/1281

When writing to UCSRnC, the value will be copied to UBRRnH unless UMSELn1 is set. This behaviour should not happen on devices that have separate locations for these registers. A workaround is to write UBRRnH after UCSRnC.

The JTD bit in the MCUCR register must be set to the desired value twice within four cycles to change its value. In the simulator the JTD bit can be written directly.

The ADC noise reduction function is not supported. Setting the ADIF flag will not wake the CPU from sleep mode.

Timer/Counter2

  • Output compare pins and FOC does not work.

  • Prescaler reset does not work correctly.

  • OCR2A/B registers are not buffered correctly in PWM mode.


Notes for ATmega645

When writing to UCSR0C, the value will be copied to UBRR0H unless bit 7 is set. This behaviour should not happen on devices that have separate locations for these registers. A workaround is to write UBRR0H after UCSR0C.

The JTD bit in the MCUCR register must be set to the desired value twice within four cycles to change its value. In the simulator the JTD bit can be written directly.

The ADC noise reduction function is not supported. Setting the ADIF flag will not wake the CPU from sleep mode.

The Watchdog is not simulated.


Notes for ATmega6450

When writing to UCSR0C, the value will be copied to UBRR0H unless bit 7 is set. This behaviour should not happen on devices that have separate locations for these registers. A workaround is to write UBRR0H after UCSR0C.

The JTD bit in the MCUCR register must be set to the desired value twice within four cycles to change its value. In the simulator the JTD bit can be written directly.

The ADC noise reduction function is not supported. Setting the ADIF flag will not wake the CPU from sleep mode.

The Watchdog is not simulated.


Notes for ATmega649

When writing to UCSR0C, the value will be copied to UBRR0H unless bit 7 is set. This behaviour should not happen on devices that have separate locations for these registers. A workaround is to write UBRR0H after UCSR0C.

The JTD bit in the MCUCR register must be set to the desired value twice within four cycles to change its value. In the simulator the JTD bit can be written directly.

The ADC noise reduction function is not supported. Setting the ADIF flag will not wake the CPU from sleep mode.

The Watchdog is not simulated.


Notes for ATmega6490

When writing to UCSR0C, the value will be copied to UBRR0H unless bit 7 is set. This behaviour should not happen on devices that have separate locations for these registers. A workaround is to write UBRR0H after UCSR0C.

The JTD bit in the MCUCR register must be set to the desired value twice within four cycles to change its value. In the simulator the JTD bit can be written directly.

The ADC noise reduction function is not supported. Setting the ADIF flag will not wake the CPU from sleep mode.

The Watchdog is not simulated.


Notes for ATmega8

The USART's UBRRH and UCSRC registers share the same I/O address. Writing to one of the registers will cause both registers to contain the new value, regardless of the value of URSEL. Reading these registers do not work as described in the datasheet.

The ADC noise reduction function is not supported. Setting the ADIF flag will not wake the CPU from sleep mode.

The Watchdog is not simulated.


Notes for ATmega8515

The USART's UBRRH and UCSRC registers share the same I/O address. Writing to one of the registers will cause both registers to contain the new value, regardless of the value of URSEL. Reading these registers do not work as described in the datasheet.

The Watchdog is not simulated.


Notes for ATmega8535

The USART's UBRRH and UCSRC registers share the same I/O address. Writing to one of the registers will cause both registers to contain the new value, regardless of the value of URSEL. Reading these registers do not work as described in the datasheet.

The ADC noise reduction function is not supported. Setting the ADIF flag will not wake the CPU from sleep mode.

The Watchdog is not simulated.


Notes for ATtiny11

The Watchdog is not simulated.


Notes for ATtiny13

The ADC noise reduction function is not supported. Setting the ADIF flag will not wake the CPU from sleep mode.


Notes for ATtiny15

The ADC noise reduction function is not supported. Setting the ADIF flag will not wake the CPU from sleep mode.

The Watchdog is not simulated.

Timer/Counter1

When using the fast peripheral clock (PCK) for Timer/Counter1, changes to the output compare pin may not be noticed if using small values for OCR1A and OCR1B.

Manually modifying OCR1B and OCR1A will update the I/O view, but will not actually modify the register values in Timer/Counter1.

It is not possible to manually turn off TOV1 or OCF1.


Notes for ATtiny22

The Watchdog is not simulated.


Notes for ATtiny24

Bit 3 of PORTB (PB3/PIN3/DDR3) is always available in the simulator, in the real device PORTB bit 3 is shared with the RESET pin, and it will not be available until the RSTDISBL (Reset Disable) fuse is programmed.

The Watchdog is not simulated.


Notes for ATtiny26

It is not possible to simulate Timer/Counter1 using the PLL clock. The sequence for enabling the PLL is simulated, but the PLL will appear to be running at the same speed as the system clock.

The ADC noise reduction function is not supported. Setting the ADIF flag will not wake the CPU from sleep mode. The initial dummy conversion after enabling ADC is not simulated.

The Watchdog is not simulated.


Notes for ATtiny261/461/861

Timer/Counter 0 and Timer/Counter 1 are not simulated.

The ADC noise reduction function is not supported. Setting the ADIF flag will not wake the CPU from sleep mode. The initial dummy conversion after enabling ADC is not simulated.

The Watchdog is not simulated.


Notes for ATtiny28

Only basic support for ATtiny28 is implemented. The specialized peripherals on this device is not yet implemented in hte simulator.

Timer/Counter

The following features are missing:

  • PA2 output on overflow and Overflow Output Modes

  • Clocking with Modulator Period

Port B

The following features are missing:

  • Low-level Input Interrupt

Modulator

The modulator is not simulated.

Watchdog

The watchdog is not simulated.


Notes for ATtiny45

Notes for ATtiny25/45/85

These devices are supported by AVR Simulator 2, and we recommend using that to avoid the issues listed below.

Timer/Counter1, including the Dead Time Generator, is currently not supported in the AVR Simulator.

The ADC noise reduction function is not supported. Setting the ADIF flag will not wake the CPU from sleep mode.

The Watchdog is not simulated.


Notes for ATtiny2313

When writing to UCSRC, the value will be copied to UBRRH unless bit 7 is also set in in the same write operation. This behaviour is erroneous on devices that have separate locations for these registers. Another workaround is to write UBRRH after UCSRC.

The Watchdog is not simulated.


Change History

What's New in AVR Studio 4.12

  • Various EEPROM fixes. EEPROM Programming Mode bits now supported. EEPROM support added for AT90S1200, AT90S2313, AT90S2323, AT90S2343, AT90S8515, ATtiny22, AT90S8535, ATmega103, ATmega161, ATmega163, ATmega32, ATmega323.

  • Data breakpoints and breakpoints with hit counts.

  • Support for ATmega640/1280/1281.

  • Partial support for ATmega406.

  • Support for AT90CAN32 and AT90CAN64.

  • Partial support for ATtiny261, ATtiny461, ATtiny861 (note: timer/counters not supported)

  • Improved execution performance.

What's New in AVR Studio 4.11 SP3

  • Support for new devices: ATmega644, ATtiny25, ATtiny85.

  • Bug fixed: ATtiny15 timer0 overflow interrupt not working.

What's New in AVR Studio 4.11 SP2

  • Support for new devices: ATmega645, ATmega6450, ATmega649, ATmega6490, ATtiny24.

  • Partial support for ATtiny28.

  • Bug fixed: Unmotivated watchdog reset when using 16-bit timers on ATmega2560/2561.

  • Bug fixed: LD Rd,Z and ST Z,Rr instructions incorrectly reported as unsupported on ATtiny11/ATtiny12/ATtiny15/ATtiny28/AT90S1200.

  • Bug fixed: ATtiny2313 Timer/Counter1 interrupt flags would be cleared causing interrupts to never happen.

What's New in AVR Studio 4.11

  • Support for additional devices: AT90PWM2, AT90PWM3, ATmega2560, ATmega2561 and ATtiny45.

  • ATtiny26: various fixes for Timer/Counter1.

  • ATtiny15: various fixes for Timer/Counter1.

  • Various fixes for most devices' Timer/Counter0: is now cycle-correct and fully functional.

  • Fixed problem with timers clearing PORT bits when output compare was not enabled.

  • Writing to PIN toggles corresponding PORT register for newer parts: AT90CAN128, ATmega165,169, 325, 329, 3250, 3290, 48/88/168, 649, ATtiny13 and ATtiny2313.

  • Added support for IVSEL flag.

  • ATmega8515: corrected prescaler on Timer/Counter0.

  • Unsupported instructions will not be executed. For instance, MUL is not available on ATtiny13.

  • Corrected cycle count for interrupts.

  • ATtiny13: ACSR bit 7 (ACD) could not be set.

  • ATmega8: Fixed maximum speed and added missing interrupt vectors.

Changes in Previous Versions

What's New in AVR Studio 4.10

  • Fast PWM (WGM 14) on ATmega128 would count to ICR+1 then stop

  • Timer0 on ATtiny13, ATtiny2313, ATmega48/88/168:

    • Prescaler fixed

    • Overflow interrupts fixed

  • Fixed bug in external interrupt settings for m48, m88 and m168.

  • Fixed pin change interrupt setting for ATtiny13.

What's New in AVR Studio 4.09

  • Added updated support for ATmega48/88/168.

  • Added support for ATmega329.

  • Fixes in ATmega128 timer1 and timer3:

    • Prescaler divisor correct and working.

    • Output Compare A, B and C interrupts and flags are set correctly.

    • OCF1/3C not cleared by writing zero.

    • Pin B, bit 7 toggled by Output Compare C.

    • FOC, channels A,B and C set correctly.

    • CTC mode toggles correctly.

    • Input capture flags and interrupts handled correctly.

    • Output compare for channels A,B and C toggled correctly.

    • Prescaler resets correctly.


Simulator2 Stimuli

Simulator2 Stimuli in AVR Studio

Introduction

The Simultor2 stimuli feature is intended to be an improvement over the stimuli/logging feature found in the old Simulator 1. It is still in early development, and more features will be added to it at a later time.

Improvements over the old simulator1 stimuli mechanism include:

  • Timing is expressed in terms of delay instead of absolute cycle counter values

  • Any I/O register can be assigned to (stimulated), not only port registers

  • Individual bits in I/O registers can be stimulated using bitwise assignments

  • Directives increase flexibility

Stimuli file format

A stimuli file is a simple ASCII plain text file containing stimuli commands, one command per line. Apart from comments (starting with '//') there are only 3 kinds of commands: Delays, assignments, and directives.

Delays

A delay is specified by an '#' character followed by the duration of the delay specified in CPU clock cycles. I.e., #20 means a delay of 20 clock cycles. Using delays is the only way of separating commands in time. Commands that are not separated by delays will be executed simultaneously (i.e., in the same clock cycle). In the current implementation stimuli are only evaluated between CPU single steps, meaning that the delay may be longer than specified if it would end in the middle of a multi-cycle instruction.

Assignments

Assignments are used to assign a new value to an I/O register (i.e., apply the actual stimuli). The following forms of assignments are currently supported:

Statement | Description
target = value | Direct assignment; set target equal to value
target |= value | Bitwise OR assignment; bits that are '1' in value will be set in target, remaining bits unchanged.
target &= value | Bitwise AND assignment; bits that are '0' in value will be cleared in target, remaining bits unchanged.
target ^= value | Bitwise XOR assignment; bits that are '1' in value will be toggled (inverted) in target, remaining bits unchanged.

For all forms of assignment, target is the name (case sensitive, names are in UPPER case) or numerical MEMORY address of an I/O register in the I/O map. Value is either a numerical constant (specified in decimal, octal, or hex according to C syntax), or it can have the form *source where source is the name or memory address of an I/O register (i.e., one can assign from one register to another). The current interpreter does not support expressions, i.e., one cannot say

GPIOR0 = *GPIOR1 + 1

Directives

A directive is initiated by a '$' character, followed by a command. Directives are used to control various aspects of stimuli execution and logging.

The currently supported directives are:

Directive | Arguments | Description
$stimulate | filename | Start reading of stimuli from a new file. The new file will be read in parallel with the current file.
$quit |  | Quit the current stimuli file, the remainder of the file will be discarded and the file is closed. (same as when hitting end of file)
$break |  | Break program execution. Stimuli file(s) remain open and stimuli will be resumed when program execution is resumed.
$repeat | number | Start a repeat loop, repeat number times until $endrep directive
$endrep |  | End of repeat loop.
$log | IO-register | Set up for logging of a register. Logging will not start until $startlog directive is executed.
$unlog | IO-register | Stop logging a register.
$startlog | filename | Start logging to named file.
$stoplog |  | Stop logging.

A log entry is generated whenever a logged I/O register changes value for whatever reason. The log format is compatible with the stimuli format; i.e., log output can be used as stimuli input. The log file will consist of delay statements and assignments.

Use from AVR Studio

The stimuli generator is started from AVR Studio using the menu selection Debug – Simulator2 Options. The stimuli file name can be typed into the text field or browsed for using the “Stimuli file” button, both located at the bottom of the options window.

The stimuli input file must be prepared in advance using a text editor. It is recommended to use the extension “.stim” for stimuli files.

Stimuli is applied when the application program is run or single-stepped. To assist debugging, the stimuli commands are echoed in AVR Studio's message output pane with a time stamp (cycle counter) as they are executed. Presently, there is no manner to disable this (apart from disabling AVR Studio “info” output altogether).

Logging can only be started by means of commands in stimuli files, there are presently no GUI facilities to set up/start logging. AVR Studio currently only supports logging to file, not to the output pane.

Known issues

Stimuli files

  • In assignments, the operator (=, etc) must be surrounded by spaces.

  • The stimuli interpreter will fail if the last line of the stimuli input file is not terminated by a newline.

  • There is no manner to assign values to 16- or 32-bit register tuples, e.g., to assign to ADC one must assign to ADCL and ADCH separately. See example in next section.

  • Error reporting leaves a lot to be desired.

  • The timing of stimuli can be a cycle or two off compared to delay specification because stimuli files are evealuated only between CPU single-steps in the current implementation.

  • Sharing violation if attempting to edit a stimuli file while open.

Example stimuli file

The following example shows how ADC conversion results can be injected into the ADC data registers, and an ADC interrupt be triggered by setting the ADIF flag in ADCSRA. This example is set up for an ATmega164 but should work on most AVR devices with an ADC. The example does not show meaningful use of ADC but illustrates how stimuli files can be used.

The example also shows use of logging and break directives.

// Initial delay

#100

// Set up logging ADC and ADCSRA to file adc.log

$log ADCL

$log ADCH

$log ADCSRA

$startlog adc.log

// start of repeat loop

$repeat 100

// Assuming TCNT1 is running, use as data for ADC

ADCL = *TCNT1L

ADCH = *TCNT1H

// Set ADIF flag in ADCSRA, this will trigger ADCC interrupt

ADCSRA |= 0x10

#30

$endrep

// Stop logging (close log file)

$stoplog

// break program execution

$break


Notes for ATmega16HVA

Timer/Counter0 and Timer/Counter1 is not supported.

The special features such as the Coulomb counter, V-ADC, Voltage Reference and Temperature Sensor, Battery Protection, FET Control are not simulated.


Notes for ATmega32C1/ATmega32M1

  • Timer/Counter 0 is not properly simulated.

  • CAN and LIN modules not simulated.


Notes for ATmega32U4

  • Timer/Counter 0 and Timer/Counter4 not simulated.

  • USB module not simulated.


Notes for ATtiny43u

This device is supported by AVR Simulator 2, and we recommend using that to avoid the issues listed below.

The Watchdog is not simulated.

Timer/Counter 1 does not work.


Notes for ATtiny48

This device is supported by AVR Simulator 2, and we recommend using that to avoid the issues listed below.

When writing to UCSR0C, the value will be copied to UBRR0H unless UMSEL01 is set. This behaviour should not happen on devices that have separate locations for these registers. A workaround is to write UBRR0H after UCSR0C.

The ADC noise reduction function is not supported. Setting the ADIF flag will not wake the CPU from sleep mode.


Notes for ATtiny167

  • Timer/Counter0 is not simulated properly.

  • LIN module not simulated.