System Settings

 
Environment Settings
Environment Variable xst ngdbuild map par
PATHEXT .COM;
.EXE;
.BAT;
.CMD;
.VBS;
.VBE;
.JS;
.JSE;
.WSF;
.WSH;
.MSC		 .COM;
.EXE;
.BAT;
.CMD;
.VBS;
.VBE;
.JS;
.JSE;
.WSF;
.WSH;
.MSC		 .COM;
.EXE;
.BAT;
.CMD;
.VBS;
.VBE;
.JS;
.JSE;
.WSF;
.WSH;
.MSC		 .COM;
.EXE;
.BAT;
.CMD;
.VBS;
.VBE;
.JS;
.JSE;
.WSF;
.WSH;
.MSC
Path C:\Xilinx\13.1\ISE_DS\ISE\\lib\nt;
C:\Xilinx\13.1\ISE_DS\ISE\\bin\nt;
C:\Xilinx\13.1\ISE_DS\PlanAhead\bin;
C:\Xilinx\13.1\ISE_DS\ISE\bin\nt;
C:\Xilinx\13.1\ISE_DS\ISE\lib\nt;
C:\Xilinx\13.1\ISE_DS\EDK\bin\nt;
C:\Xilinx\13.1\ISE_DS\EDK\lib\nt;
C:\Xilinx\13.1\ISE_DS\EDK\gnu\microblaze\nt\bin;
C:\Xilinx\13.1\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin;
C:\Xilinx\13.1\ISE_DS\EDK\gnuwin\bin;
C:\Xilinx\13.1\ISE_DS\common\bin\nt;
C:\Xilinx\13.1\ISE_DS\common\lib\nt;
C:\Xilinx\11.1\PlanAhead\bin;
C:\Xilinx\11.1\common\bin\nt;
C:\Xilinx\11.1\ISE\bin\nt;
C:\Xilinx\11.1\ISE\lib\nt;
C:\Windows\system32;
C:\Windows;
C:\Windows\System32\Wbem;
C:\Windows\System32\WindowsPowerShell\v1.0\;
c:\altera\11.1sp2\quartus\bin;
C:\Program Files\Microchip\MPLAB C32 Suite\bin;
C:\Program Files\Microchip\MPLAB IDE\VDI;
C:\PROGRA~1\PICC;
C:\OrCAD\OrCAD_16.3_Demo\tools\bin;
C:\OrCAD\OrCAD_16.3_Demo\tools\specctra\bin;
C:\OrCAD\OrCAD_16.3_Demo\tools\PSpice;
C:\OrCAD\OrCAD_16.3_Demo\tools\PSpice\Library;
C:\OrCAD\OrCAD_16.3_Demo\tools\Capture;
C:\OrCAD\OrCAD_16.3_Demo\tools\fet\bin;
C:\OrCAD\OrCAD_16.3_Demo\tools\pcb\bin;
C:\OrCAD\OrCAD_16.3_Demo\OpenAccess\bin\win32\opt		 C:\Xilinx\13.1\ISE_DS\ISE\\lib\nt;
C:\Xilinx\13.1\ISE_DS\ISE\\bin\nt;
C:\Xilinx\13.1\ISE_DS\PlanAhead\bin;
C:\Xilinx\13.1\ISE_DS\ISE\bin\nt;
C:\Xilinx\13.1\ISE_DS\ISE\lib\nt;
C:\Xilinx\13.1\ISE_DS\EDK\bin\nt;
C:\Xilinx\13.1\ISE_DS\EDK\lib\nt;
C:\Xilinx\13.1\ISE_DS\EDK\gnu\microblaze\nt\bin;
C:\Xilinx\13.1\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin;
C:\Xilinx\13.1\ISE_DS\EDK\gnuwin\bin;
C:\Xilinx\13.1\ISE_DS\common\bin\nt;
C:\Xilinx\13.1\ISE_DS\common\lib\nt;
C:\Xilinx\11.1\PlanAhead\bin;
C:\Xilinx\11.1\common\bin\nt;
C:\Xilinx\11.1\ISE\bin\nt;
C:\Xilinx\11.1\ISE\lib\nt;
C:\Windows\system32;
C:\Windows;
C:\Windows\System32\Wbem;
C:\Windows\System32\WindowsPowerShell\v1.0\;
c:\altera\11.1sp2\quartus\bin;
C:\Program Files\Microchip\MPLAB C32 Suite\bin;
C:\Program Files\Microchip\MPLAB IDE\VDI;
C:\PROGRA~1\PICC;
C:\OrCAD\OrCAD_16.3_Demo\tools\bin;
C:\OrCAD\OrCAD_16.3_Demo\tools\specctra\bin;
C:\OrCAD\OrCAD_16.3_Demo\tools\PSpice;
C:\OrCAD\OrCAD_16.3_Demo\tools\PSpice\Library;
C:\OrCAD\OrCAD_16.3_Demo\tools\Capture;
C:\OrCAD\OrCAD_16.3_Demo\tools\fet\bin;
C:\OrCAD\OrCAD_16.3_Demo\tools\pcb\bin;
C:\OrCAD\OrCAD_16.3_Demo\OpenAccess\bin\win32\opt		 C:\Xilinx\13.1\ISE_DS\ISE\\lib\nt;
C:\Xilinx\13.1\ISE_DS\ISE\\bin\nt;
C:\Xilinx\13.1\ISE_DS\PlanAhead\bin;
C:\Xilinx\13.1\ISE_DS\ISE\bin\nt;
C:\Xilinx\13.1\ISE_DS\ISE\lib\nt;
C:\Xilinx\13.1\ISE_DS\EDK\bin\nt;
C:\Xilinx\13.1\ISE_DS\EDK\lib\nt;
C:\Xilinx\13.1\ISE_DS\EDK\gnu\microblaze\nt\bin;
C:\Xilinx\13.1\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin;
C:\Xilinx\13.1\ISE_DS\EDK\gnuwin\bin;
C:\Xilinx\13.1\ISE_DS\common\bin\nt;
C:\Xilinx\13.1\ISE_DS\common\lib\nt;
C:\Xilinx\11.1\PlanAhead\bin;
C:\Xilinx\11.1\common\bin\nt;
C:\Xilinx\11.1\ISE\bin\nt;
C:\Xilinx\11.1\ISE\lib\nt;
C:\Windows\system32;
C:\Windows;
C:\Windows\System32\Wbem;
C:\Windows\System32\WindowsPowerShell\v1.0\;
c:\altera\11.1sp2\quartus\bin;
C:\Program Files\Microchip\MPLAB C32 Suite\bin;
C:\Program Files\Microchip\MPLAB IDE\VDI;
C:\PROGRA~1\PICC;
C:\OrCAD\OrCAD_16.3_Demo\tools\bin;
C:\OrCAD\OrCAD_16.3_Demo\tools\specctra\bin;
C:\OrCAD\OrCAD_16.3_Demo\tools\PSpice;
C:\OrCAD\OrCAD_16.3_Demo\tools\PSpice\Library;
C:\OrCAD\OrCAD_16.3_Demo\tools\Capture;
C:\OrCAD\OrCAD_16.3_Demo\tools\fet\bin;
C:\OrCAD\OrCAD_16.3_Demo\tools\pcb\bin;
C:\OrCAD\OrCAD_16.3_Demo\OpenAccess\bin\win32\opt		 C:\Xilinx\13.1\ISE_DS\ISE\\lib\nt;
C:\Xilinx\13.1\ISE_DS\ISE\\bin\nt;
C:\Xilinx\13.1\ISE_DS\PlanAhead\bin;
C:\Xilinx\13.1\ISE_DS\ISE\bin\nt;
C:\Xilinx\13.1\ISE_DS\ISE\lib\nt;
C:\Xilinx\13.1\ISE_DS\EDK\bin\nt;
C:\Xilinx\13.1\ISE_DS\EDK\lib\nt;
C:\Xilinx\13.1\ISE_DS\EDK\gnu\microblaze\nt\bin;
C:\Xilinx\13.1\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin;
C:\Xilinx\13.1\ISE_DS\EDK\gnuwin\bin;
C:\Xilinx\13.1\ISE_DS\common\bin\nt;
C:\Xilinx\13.1\ISE_DS\common\lib\nt;
C:\Xilinx\11.1\PlanAhead\bin;
C:\Xilinx\11.1\common\bin\nt;
C:\Xilinx\11.1\ISE\bin\nt;
C:\Xilinx\11.1\ISE\lib\nt;
C:\Windows\system32;
C:\Windows;
C:\Windows\System32\Wbem;
C:\Windows\System32\WindowsPowerShell\v1.0\;
c:\altera\11.1sp2\quartus\bin;
C:\Program Files\Microchip\MPLAB C32 Suite\bin;
C:\Program Files\Microchip\MPLAB IDE\VDI;
C:\PROGRA~1\PICC;
C:\OrCAD\OrCAD_16.3_Demo\tools\bin;
C:\OrCAD\OrCAD_16.3_Demo\tools\specctra\bin;
C:\OrCAD\OrCAD_16.3_Demo\tools\PSpice;
C:\OrCAD\OrCAD_16.3_Demo\tools\PSpice\Library;
C:\OrCAD\OrCAD_16.3_Demo\tools\Capture;
C:\OrCAD\OrCAD_16.3_Demo\tools\fet\bin;
C:\OrCAD\OrCAD_16.3_Demo\tools\pcb\bin;
C:\OrCAD\OrCAD_16.3_Demo\OpenAccess\bin\win32\opt
XILINX C:\Xilinx\13.1\ISE_DS\ISE\ C:\Xilinx\13.1\ISE_DS\ISE\ C:\Xilinx\13.1\ISE_DS\ISE\ C:\Xilinx\13.1\ISE_DS\ISE\
XILINX_DSP C:\Xilinx\13.1\ISE_DS\ISE C:\Xilinx\13.1\ISE_DS\ISE C:\Xilinx\13.1\ISE_DS\ISE C:\Xilinx\13.1\ISE_DS\ISE
XILINX_EDK C:\Xilinx\13.1\ISE_DS\EDK C:\Xilinx\13.1\ISE_DS\EDK C:\Xilinx\13.1\ISE_DS\EDK C:\Xilinx\13.1\ISE_DS\EDK
XILINX_PLANAHEAD C:\Xilinx\13.1\ISE_DS\PlanAhead C:\Xilinx\13.1\ISE_DS\PlanAhead C:\Xilinx\13.1\ISE_DS\PlanAhead C:\Xilinx\13.1\ISE_DS\PlanAhead
 
Synthesis Property Settings
Switch Name Property Name Value Default Value
-ifn   Filter.prj  
-ifmt   mixed MIXED
-ofn   Filter  
-ofmt   NGC NGC
-p   xc3s400-4-fg456  
-top   Filter  
-opt_mode Optimization Goal Speed SPEED
-opt_level Optimization Effort 1 1
-iuc Use synthesis Constraints File NO NO
-keep_hierarchy Keep Hierarchy No NO
-netlist_hierarchy Netlist Hierarchy As_Optimized as_optimized
-rtlview Generate RTL Schematic Yes NO
-glob_opt Global Optimization Goal AllClockNets ALLCLOCKNETS
-read_cores Read Cores YES YES
-sd Cores Search Directories {"ipcore_dir" }  
-write_timing_constraints Write Timing Constraints NO NO
-cross_clock_analysis Cross Clock Analysis NO NO
-bus_delimiter Bus Delimiter <> <>
-slice_utilization_ratio Slice Utilization Ratio 100 100%
-bram_utilization_ratio BRAM Utilization Ratio 100 100%
-verilog2001 Verilog 2001 YES YES
-fsm_extract   YES YES
-fsm_encoding   Auto AUTO
-safe_implementation   No NO
-fsm_style   LUT LUT
-ram_extract   Yes YES
-ram_style   Auto AUTO
-rom_extract   Yes YES
-shreg_extract   YES YES
-rom_style   Auto AUTO
-auto_bram_packing   NO NO
-resource_sharing   YES YES
-async_to_sync   NO NO
-mult_style   Auto AUTO
-iobuf   YES YES
-max_fanout   500 500
-bufg   8 8
-register_duplication   YES YES
-register_balancing   No NO
-optimize_primitives   NO NO
-use_clock_enable   Yes YES
-use_sync_set   Yes YES
-use_sync_reset   Yes YES
-iob   Auto AUTO
-equivalent_register_removal   YES YES
-slice_utilization_ratio_maxmargin   5 0%
 
Translation Property Settings
Switch Name Property Name Value Default Value
-intstyle   ise None
-dd   _ngo None
-p   xc3s400-fg456-4 None
-sd Macro Search Path ipcore_dir None
 
Map Property Settings
Switch Name Property Name Value Default Value
-ir Use RLOC Constraints OFF OFF
-cm Optimization Strategy (Cover Mode) area area
-intstyle   ise None
-o   Filter_map.ncd None
-pr Pack I/O Registers/Latches into IOBs off off
-p   xc3s400-fg456-4 None
 
Place and Route Property Settings
Switch Name Property Name Value Default Value
-t   1 1
-intstyle   ise  
-ol Place & Route Effort Level (Overall) high std
-w   true false
 
Operating System Information
Operating System Information xst ngdbuild map par
CPU Architecture/Speed Intel(R) Core(TM)2 Duo CPU E8400 @ 3.00GHz/2997 MHz Intel(R) Core(TM)2 Duo CPU E8400 @ 3.00GHz/2997 MHz Intel(R) Core(TM)2 Duo CPU E8400 @ 3.00GHz/2997 MHz Intel(R) Core(TM)2 Duo CPU E8400 @ 3.00GHz/2997 MHz
Host PC-3DT06 PC-3DT06 PC-3DT06 PC-3DT06
OS Name Microsoft Windows 7 , 32-bit Microsoft Windows 7 , 32-bit Microsoft Windows 7 , 32-bit Microsoft Windows 7 , 32-bit
OS Release Service Pack 1 (build 7601) Service Pack 1 (build 7601) Service Pack 1 (build 7601) Service Pack 1 (build 7601)