Design Name | Test |
Device, Speed (SpeedFile Version) | XC9572XL, -10 (3.0) |
Date Created | Mon Jun 18 16:55:34 2012 |
Created By | Timing Report Generator: version P.15xf |
Copyright | Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. |
Notes and Warnings |
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Note: This design contains no timing constraints. |
Note: A default set of constraints using a delay of 0.000ns will be used for analysis. |
Performance Summary |
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Constraint Name | Requirement (ns) | Delay (ns) | Paths | Paths Failing |
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AUTO_TS_F2F | 0.0 | 0.0 | 0 | 0 |
AUTO_TS_P2P | 0.0 | 0.0 | 0 | 0 |
AUTO_TS_P2F | 0.0 | 0.0 | 0 | 0 |
AUTO_TS_F2P | 0.0 | 0.0 | 0 | 0 |
Path | Requirement (ns) | Delay (ns) | Slack (ns) |
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Path | Requirement (ns) | Delay (ns) | Slack (ns) |
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Path | Requirement (ns) | Delay (ns) | Slack (ns) |
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Path | Requirement (ns) | Delay (ns) | Slack (ns) |
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Source Pad | Destination Pad | Delay |
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